PIC24EP256GU810-I Datasheet, PDF (151/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 7-1: SR: CPU STATUS REGISTER⁽¹⁾
R/W-0
OA
bit 15
R/W-0
OB
R/W-0
SA
R/W-0
SB
R/C-0
OAB
R/W-0⁽³⁾
R/W-0⁽³⁾
R/W-0⁽³⁾
R-0
IPL<2:0>⁽²⁾
RA
bit 7
R/W-0
N
R/C-0
SAB
R/W-0
OV
R-0
DA
R/W-0
Z
R/W-0
DC
bit 8
R/W-0
C
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits^(2,3)
111 = CPU Interrupt Priority Level is 7 (15, user interrupts are disabled)
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
Note 1:
2:
3:
For complete register details, see Register 3-1: “SR: CPU Status Register”.
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
 2009-2012 Microchip Technology Inc.
DS70616G-page 151