PIC24EP256GU810-I Datasheet, PDF (160/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
In addition, DMA transfers can be triggered by timers
as well as external interrupts. Each DMA channel is
unidirectional. Two DMA channels must be allocated to
read and write to a peripheral. If more than one channel
receive a request to transfer data, a simple fixed priority
scheme, based on channel number, dictates which
channel completes the transfer and which channel, or
channels, are left pending. Each DMA channel moves
a block of data, after which it generates an interrupt to
the CPU to indicate that the block is available for
processing.
The DMA controller provides these functional
capabilities:
• Up to 15 DMA Channels
• Register Indirect With Post-Increment Addressing
mode
• Register Indirect Without Post-Increment
Addressing mode
• Peripheral Indirect Addressing mode (peripheral
generates destination address)
• CPU Interrupt after Half or Full Block Transfer
Complete
• Byte or Word Transfers
• Fixed Priority Channel Arbitration
• Manual (software) or Automatic (peripheral DMA
requests) Transfer Initiation
• One-Shot or Auto-Repeat Block Transfer modes
• Ping-Pong mode (automatic switch between two
DPSRAM start addresses after each block
transfer complete)
• DMA Request for Each Channel can be Selected
from Any Supported Interrupt Source
• Debug Support Features
The peripherals that can utilize DMA are listed in
Table 8-1.
TABLE 8-1: DMA CHANNEL TO PERIPHERAL ASSOCIATIONS
Peripheral to DMA Association
DMAxREQ Register
IRQSEL<7:0> Bits
DMAxPAD Register
(Values to Read from
Peripheral)
DMAxPAD Register
(Values to Write to
Peripheral)
INT0 – External Interrupt 0
IC1 – Input Capture 1
IC2 – Input Capture 2
IC3 – Input Capture 3
IC4 – Input Capture 4
OC1 – Output Compare 1
OC2 – Output Compare 2
OC3 – Output Compare 3
OC4 – Output Compare 4
TMR2 – Timer2
TMR3 – Timer3
TMR4 – Timer4
TMR5 – Timer5
SPI1 Transfer Done
SPI2 Transfer Done
SPI3 Transfer Done
SPI4 Transfer Done
UART1RX – UART1 Receiver
UART1TX – UART1 Transmitter
UART2RX – UART2 Receiver
UART2TX – UART2 Transmitter
UART3RX – UART3 Receiver
UART3TX – UART3 Transmitter
00000000
00000001
00000101
00100101
00100110
00000010
00000110
00011001
00011010
00000111
00001000
00011011
00011100
00001010
00100001
01011011
01111011
00001011
00001100
00011110
00011111
01010010
01010011
—
0x0144 (IC1BUF)
0x014C (IC2BUF)
0x0154 (IC3BUF)
0x015C (IC4BUF)
—
—
—
—
—
—
—
—
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x02A8 (SPI3BUF)
0x02C8 (SPI4BUF)
0x0226 (U1RXREG)
—
0x0236 (U2RXREG)
—
0x0256 (U3RXREG)
—
—
—
—
—
—
0x0906 (OC1R)
0x0904 (OC1RS)
0x0910 (OC2R)
0x090E (OC2RS)
0x091A (OC3R)
0x0918 (OC3RS)
0x0924 (OC4R)
0x0922 (OC4RS)
—
—
—
—
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x02A8 (SPI3BUF)
0x02C8 (SPI4BUF)
—
0x0224 (U1TXREG)
—
0x0234 (U2TXREG)
—
0x0254 (U3TXREG)
DS70616G-page 160
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