PIC24EP256GU810-I Datasheet, PDF (471/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 28-2: PMMODE: PARALLEL MASTER PORT MODE REGISTER
R-0
BUSY
bit 15
R/W-0
R/W-0
IRQM<1:0>
R/W-0
R/W-0
INCM<1:0>
R/W-0
MODE16
R/W-0
R/W-0
MODE<1:0>
bit 8
R/W-0
R/W-0
WAITB<1:0>^(1,2,3)
bit 7
R/W-0
R/W-0
R/W-0
WAITM<3:0>
R/W-0
R/W-0
R/W-0
WAITE<1:0>^(1,2,3)
bit 0
Legend:
R = Readable bit
-n = Value at Reset
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-13
bit 12-11
bit 10
bit 9-8
bit 7-6
bit 5-2
Note 1:
2:
3:
BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
IRQM<1:0>: Interrupt Request Mode bits
11 = Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP
mode), or on a read/write operation when PMA<1:0> = 11 (Addressable PSP mode only)
10 = Reserved
01 = Interrupt is generated at the end of the read/write cycle
00 = No Interrupt is generated
INCM<1:0>: Increment Mode bits
11 = PSP read and write buffers auto-increment (Legacy PSP mode only)
10 = Decrements ADDR by 1 every read/write cycle
01 = Increments ADDR by 1 every read/write cycle
00 = No increment or decrement of address
MODE16: Parallel Master Port Mode 8/16-Bit Mode bit
1 = 16-bit mode: data register is 16 bits, a read/write to the data register invokes two 8-bit transfers
0 = 8-bit mode: data register is 8 bits, a read/write to the data register invokes one 8-bit transfer
MODE<1:0>: Parallel Master Port Mode Select bits
11 = Master Mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)
10 = Master Mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)
01 = Enhanced PSP, controls signals (PMRD, PMWR, PMCSx, PMD<7:0> and PMA<1:0>)
00 = Legacy Parallel Slave Port, controls signals (PMRD, PMWR, PMCSx and PMD<7:0>)
WAITB<1:0>: Data Setup to Read/Write/Address Phase Wait State Configuration bits^(1,2,3)
11 = Data wait of 4 TP (demultiplexed/multiplexed); address phase of 4 TP (multiplexed)
10 = Data wait of 3 TP (demultiplexed/multiplexed); address phase of 3 TP (multiplexed)
01 = Data wait of 2 TP (demultiplexed/multiplexed); address phase of 2 TP (multiplexed)
00 = Data wait of 1 TP (demultiplexed/multiplexed); address phase of 1 TP (multiplexed)
WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits
1111 = Wait of additional 15 TP
•
•
•
0001 = Wait of additional 1 TP
0000 = No additional Wait cycles (operation forced into one TP)
The applied Wait state depends on whether data and address are multiplexed or demultiplexed. See
Section 28.4.1.8. “Wait States” in Section 28. “Parallel Master Port (PMP)” (DS70576) in the
“dsPIC33E/PIC24E Family Reference Manual” for more information.
WAITB<1:0> and WAITE<1:0> bits are ignored whenever WAITM<3:0> = 0000.
TP = 1/FP.
 2009-2012 Microchip Technology Inc.
DS70616G-page 471