PIC24EP256GU810-I Datasheet, PDF (188/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 9-5:
R/W-0
ENAPLL
bit 15
ACLKCON3: AUXILIARY CLOCK CONTROL REGISTER 3^(1,2)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SELACLK
AOSCMD<1:0>
ASRCSEL FRCSEL
U-0
—
bit 8
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
APLLPOST<2:0>
—
—
APLLPRE<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-11
bit 10
bit 9
bit 8
bit 7-5
bit 4-3
bit 2-0
ENAPLL: Enable Auxiliary PLL (APLL) and Select APLL as USB Clock Source bit
1 = APLL is enabled, the USB clock source is the APLL output
0 = APLL is disabled, the USB clock source is the input clock to the APLL
Unimplemented: Read as ‘0’
SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit
1 = Auxiliary PLL or oscillator provides the source clock for auxiliary clock divider
0 = Primary PLL provides the source clock for auxiliary clock divider
AOSCMD<1:0>: Auxiliary Oscillator Mode bits
11 = EC (External Clock) Oscillator mode select
10 = XT (Crystal) Oscillator mode select
01 = HS (High-Speed) Oscillator mode select
00 = Auxiliary Oscillator disabled (default)
ASRCSEL: Select Reference Clock Source for APLL bit
1 = Primary Oscillator is the clock source for APLL
0 = Auxiliary Oscillator is the clock source for APLL
FRCSEL: Select FRC as Reference Clock Source for APLL bit
1 = FRC is the clock source for APLL
0 = Auxiliary Oscillator or Primary Oscillator is the clock source for APLL (determined by ASRCSEL bit)
Unimplemented: Read as ‘0’
APLLPOST<2:0>: Select PLL VCO Output Divider bits
111 = Divided by 1
110 = Divided by 2
101 = Divided by 4
100 = Divided by 8
011 = Divided by 16
010 = Divided by 32
001 = Divided by 64
000 = Divided by 256 (default)
Unimplemented: Read as ‘0’
APLLPRE<2:0>: PLL Phase Detector Input Divider bits
111 = Divided by 12
110 = Divided by 10
101 = Divided by 6
100 = Divided by 5
011 = Divided by 4
010 = Divided by 3
001 = Divided by 2
000 = Divided by 1 (default)
Note 1: This register resets only on a Power-on Reset (POR).
2: This register is only available on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices.
DS70616G-page 188
 2009-2012 Microchip Technology Inc.