PIC24EP256GU810-I Datasheet, PDF (477/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
29.0 SPECIAL FEATURES
Note:
This data sheet summarizes the features of
the dsPIC33EPXXX(GP/MC/MU)806/810/
814 and PIC24EPXXX(GP/GU)810/814
families of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
dsPIC33EPXXX(GP/MC/MU)806/810/814
and
PIC24EPXXX(GP/GU)810/814 devices include
several features intended to maximize application
flexibility and reliability, and minimize cost through
elimination of external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
29.1 Configuration Bits
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 devices provide
nonvolatile memory implementation for device Configu-
ration bits. Refer to Section 30. “Device Configuration”
(DS70618) of the “dsPIC33E/PIC24E Family Reference
Manual” for more information on this implementation.
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped,
starting at program memory location, 0xF80000.
The individual Configuration bit descriptions for the
Configuration registers are shown in Table 29-2.
Note that address, 0xF80000, is beyond the user
program memory space. It belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using table reads and table writes.
To prevent inadvertent configuration changes during
code execution, some programmable Configuration
bits are write-once. For such bits, changing a device
configuration requires that the device be reset. For
other Configuration bits, the device configuration
changes immediately after an RTSP operation. The
RTSP effect column in Table 29-2 indicates when the
device configuration changes after a bit is modified
using RTSP.
The device Configuration register map is shown in
Table 29-1.
TABLE 29-1: DEVICE CONFIGURATION REGISTER MAP
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
0xF80000 Reserved
—
—
—
—
—
—
—
—
0xF80002 Reserved
—
—
—
—
—
—
—
—
0xF80004 FGS
—
—
GSSK<1:0>
—
—
GSS GWRP
0xF80006 FOSCSEL IESO
—
—
—
—
FNOSC<2:0>
0xF80008 FOSC
FCKSM<1:0> IOL1WAY
—
—
OSCIOFNC POSCMD<1:0>
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
FWDTEN WINDIS
—
—
Reserved⁽¹⁾
PLLKEN
ALTI2C2
JTAGEN
WDTPRE
ALTI2C1 BOREN⁽²⁾
Reserved⁽¹⁾
—
WDTPOST<3:0>
FPWRT<2:0>
RSTPRI
ICS<1:0>
0xF80010 FAS
—
—
APLK<1:0>
—
—
APL AWRP
0xF80012 FUID0
User Unit ID Byte 0
Legend: — = unimplemented bit, read as ‘0’
Note 1: These bits are reserved for use by development tools and must be programmed as ‘1’.
2: BOR should always be enabled for proper operation (BOREN = 1).
 2009-2012 Microchip Technology Inc.
DS70616G-page 477