PIC24EP256GU810-I Datasheet, PDF (350/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER
R-0, HSC R-0, HSC
U-0
U-0
ACKSTAT TRSTAT
—
—
bit 15
U-0
R/C-0, HS
—
BCL
R-0, HSC
GCSTAT
R-0, HSC
ADD10
bit 8
R/C-0, HS
IWCOL
bit 7
R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC
I2COV
D_A
P
S
R-0, HSC
R_W
R-0, HSC
RBF
R-0, HSC
TBF
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13-11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
ACKSTAT: Acknowledge Status bit
(when operating as I²C™ master, applicable to master transmit operation)
1 = NACK received from slave
0 = ACK received from slave
Hardware is set or clear at the end of a slave Acknowledge.
TRSTAT: Transmit Status bit (when operating as I²C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware is set at the beginning of a master transmission. Hardware is clear at the end of a slave
Acknowledge.
Unimplemented: Read as ‘0’
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware is set at detection of a bus collision.
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware is set when an address matches the general call address. Hardware is clear at a Stop detection.
ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware is set at a match of the 2nd byte of a matched 10-bit address. Hardware is clear at a Stop detection.
IWCOL: Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I²C module is busy
0 = No collision
Hardware is set at an occurrence of a write to I2CxTRN while busy (cleared by software).
I2COV: I2Cx Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
D_A: Data/Address bit (when operating as I²C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was a device address
Hardware is clear at a device address match. Hardware is set by reception of a slave byte.
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware is set or clear when a Start, Repeated Start or Stop is detected.
DS70616G-page 350
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