PIC24EP256GU810-I Datasheet, PDF (179/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
9.1 CPU Clocking System
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 family of devices
provides seven system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with Phase-Locked Loop (PLL)
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Secondary (LP) Oscillator
• Low-Power RC (LPRC) Oscillator
• FRC Oscillator with postscaler
FIGURE 9-2:
PLL BLOCK DIAGRAM
Instruction execution speed or device operating
frequency, FCY, is given by Equation 9-1.
EQUATION 9-1: DEVICE OPERATING
FREQUENCY
FCY = FOSC/2
Figure 9-2 is a block diagram of the PLL module.
Equation 9-2 provides the relation between input
frequency (FIN) and output frequency (FOSC).
Equation 9-3 provides the relation between input
frequency (FIN) and VCO frequency (FVCO).
0.8 MHz < FREF < 8.0 MHz
FIN
÷ N1
FREF
PFD
120 MHZ < FVCO < 340 MHZ
FOSC < 120 MHz @ +125ºC
FOSC < 140 MHz @ +85ºC
VCO
FVCO
÷ N2
FOSC
PLLPRE<4:0>
PLLPOST<2:0>
÷M
PLLDIV<8:0>
EQUATION 9-2: FOSC CALCULATION
FOSC
=
F
I
N



N^-----1----M^-----N^{----2--}
=
FIN



^---P^----L^----L^---P^----R^----E^------+^-P---2-L---^-L--^{-D----2-I--V-}^--P^--+--L^---2-L^---P^----O^-----S^---T^-----+^-----1----
Where,
N1 = PLLPRE + 2
N2 = 2 x (PLLPOST + 1)
M = PLLDIV + 2
EQUATION 9-3: FVCO CALCULATION
FVCO
=
FIN



N^{--M---1-}
=
FIN  _{}-^--_PP----_LL----_LL---_P-^D---_R--^I--^VE-----⁺-₊----22---^-_{}
 2009-2012 Microchip Technology Inc.
DS70616G-page 179