PIC24EP256GU810-I Datasheet, PDF (284/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0
—
bit 15
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
R/W-0
IC32
bit 8
R/W-0
R/W/HS-0
U-0
ICTRIG⁽²⁾ TRIGSTAT⁽³⁾
—
bit 7
R/W-0
R/W-1
R/W-1
R/W-0
SYNCSEL<4:0>⁽⁴⁾
R/W-1
bit 0
Legend:
R = Readable bit
-n = Value at POR
HS = Set by Hardware
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
bit 15-9
bit 8
bit 7
bit 6
bit 5
Unimplemented: Read as ‘0’
IC32: 32-Bit Timer Mode Select bit (Cascade mode)
1 = ODD IC and EVEN IC form a single 32-bit input capture module⁽¹⁾
0 = Cascade module operation is disabled
ICTRIG: Trigger Operation Select bit⁽²⁾
1 = Input source is used to trigger the input capture timer (Trigger mode)
0 = Input source is used to synchronize the input capture timer to a timer of another module
(Synchronization mode)
TRIGSTAT: Timer Trigger Status bit⁽³⁾
1 = ICxTMR has been triggered and is running
0 = ICxTMR has not been triggered and is being held clear
Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
5:
The IC32 bit in both the ODD and EVEN IC must be set to enable Cascade mode.
The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
This bit is set by the selected input source (selected by the SYNCSEL<4:0> bits); it can be read, set and
cleared in software.
Do not use the ICx module as its own Sync or Trigger source.
This option should only be selected as a trigger source and not as a synchronization source.
DS70616G-page 284
 2009-2012 Microchip Technology Inc.