T8207 Datasheet, PDF (98/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
14 Registers (continued)
Table 58. Main Configuration/Control (MCFCT) (0110h)
Name
cntl_cell_rd
cntl_cell_wr
cb_req_pr
clp_fill_limit
cell_drop_en
inv_crc
cb_rx_en
slave_en
Reserved
Bit Pos.
0
1
3:2
Type
WO
RW
RW
Reset
Description
0 Control Cell Has Been Read. Write ‘1’ to this bit after a control
cell is read from the control cell FIFO. The ‘1’ will pulse for one
clock cycle and will clear to ‘0’ automatically.
0 Control Cell Written in Control Cell Memory. Write ‘1’ to this bit
after a control cell is written in the control cell memory. This bit is
automatically cleared when the cell is transmitted to the cell bus.
0 Cell Bus Request Priority. These bits indicate the priority of stan-
dard requests sent on the cell bus as follows:
10:4 RW
11
RW
12
RW
13
RW
14
RW
15
RO
“00” = disabled, receives cells from cell bus but cannot transmit
“01” = low priority
“10” = medium priority
“11” = high priority
0 CLP Fill Limit. These bits indicate the TX PHY FIFO fill level at
which cells with their CLP bit set to one will be discarded.
0 Cell Drop Enable. If this bit is one, incoming cells with their CLP
bit set to one will be discarded when the TX PHY FIFO fill limit pro-
grammed in the clp_fill_limit bits is reached.
0 Invert CRC. If this bit is one, the CRC-4 in the routing header is
inverted before transmission to the cell bus. This bit is used to sim-
ulate errors.
0 Cell Bus Receive Enable. If this bit is ‘1,’ cells are received from
the cell bus. If ‘0,’ cells are not accepted.
1 Slave Enable. If this bit is ‘1,’ the T8207 is configured as a slave in
shared UTOPIA mode. The default value of this bit is ‘1.’ Clear this
bit if shared UTOPIA is not used. For shared UTOPIA, only one of
the two devices may have this bit cleared. Dynamically changing
this bit will cause cell loss. When this bit is ‘1,’ u_rxenb*[0] and
u_rxenb*[3:1] become inputs.
0 Reserved.
Table 59. Main Configuration 2 (MCF2) (0112h)
Name
addr_clav_en
Bit Pos. Type
2:0 RW
Reset
Description
0 UTOPIA Address, Cell Available, and Enable Signals. These bits
configure the number of address, cell available, and enable signals
on the UTOPIA bus as follows (see Section 9.6 on page 50):
Reserved
“000” = 0 ADDR, 4 CLAV, 4 ENB “100” = 2 ADDR, 2 CLAV, 2 ENB
“001” = 4 ADDR, 1 CLAV, 1 ENB “101” = 2 ADDR, 4 CLAV, 4 ENB
“010” = 1 ADDR, 4 CLAV, 4 ENB “110” = 3 ADDR, 1 CLAV, 1 ENB
“011” = 4 ADDR, 2 CLAV, 2 ENB “111” = 3 ADDR, 2 CLAV, 2 ENB
3
RO
0 Reserved.
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