T8207 Datasheet, PDF (58/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
10 Cell Bus Interface (continued)
Devices on the cell bus make their requests during the first cycle of each frame. In 16-user mode, each device
asserts a request every frame. In 32-user mode, each device asserts a request every two frames. In 32-user mode,
devices with unit addresses 0 through 15 assert their requests during the even frames, and devices with unit
addresses 16 through 31 assert their requests during the odd frames. During cycle 0 of their assigned frame,
each device drives two of the 32 data bits available. The position of the two request bits for each device is based
on the device’s unit address. The assigned bit positions for each device are illustrated in Figure 14 and Figure 15
for 16-user and 32-user modes, respectively. For example, in the figures, the device with unit address 0 makes
its requests using the 2 bits labeled as U0. Two bits, instead of one, are used for each device so the priority
of the request may be included. The priority of the request is set up using the cb_req_pr bits in the main configura-
tion/control register (address 0110h). See Table 58 in Section 14.3, Extended Memory Registers, for more informa-
tion.
During clock cycles 1 through 14, the device that was granted the bus at the end of the previous frame sends its
bus cell. The bus cell sent includes the cell bus routing header, the tandem routing header, and the original
UTOPIA cell with the header error check (HEC) byte removed. The HEC byte is removed because the cell bus
does its own error check over the complete cell using the bit interleave parity byte. The HEC byte is recreated and
inserted before the received cell is placed on the UTOPIA bus.
The cell bus routing header indicates the type of the cell (data, control, loopback) and its destination (single, multi-
cast, broadcast). See Section 10.3, Cell Bus Routing Headers, for more information on the cell bus routing header
structure. The optional tandem routing header is configured by the user.
The 32 bits of the grant section of the frame (clock cycle 15) includes the bit interleave parity (BIP-8) byte, the grant
parity bit, the grant enable bit, and the grant number. The most significant 8 bits of the grant section of the frame is
the BIP-8 byte. The BIP-8 byte is calculated over 54 bytes starting with the first tandem routing header byte and
ending with the last payload byte. To calculate this bit interleave parity, an exclusive-OR operation is performed on
the first byte of the tandem routing header and the value “11111111.” The exclusive-OR operation then is performed
on this result and the following byte. The operation is then repeated with every successive byte through the last
data byte of the payload. The resulting byte becomes the BIP-8 byte of the grant section. The next 17 bits of the
grant section are unused. The least significant 7 bits of the grant section are used to grant transmission requests.
The grant number is located in the least significant 5 bits of the grant section and is the unit address of the device
that transmits a cell during the next frame. The grant enable, bit 5, is an active-high signal that indicates if the grant
is valid. Finally, the grant parity, bit 6, is the odd parity check calculated over the other six grant bits.
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