T8207 Datasheet, PDF (25/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
6 Microprocessor Interface (continued)
6.3.2 CelXpres T8207 Access Performance
The times represented in the following table reflect access times for various microprocessor interface reads and
writes. For direct access registers, the values represent the time until the rdy_dtack signal transitions indicating the
data transfer portion of the access is complete. For accesses to extended memory, the values represent the time
from the completion of a write to register 34h until the ext_strt_acc bit is cleared.
The actual times are dependent on the frequency of the pclk and mclk clocks (see Section 5, PLL Configuration).
The terms pclkp and mclkp in the table represent the period of pclk and mclk, respectively, in ns.
Table 10. Access Times
Description
Min
Typ
Max
Unit
Read/Write to 28h—3Dh
4 x pclkp
5 x pclkp
5 x pclkp + 30
ns
Reads to:
60h—93h,
A0h—D7h,
E0h—FFh
(direct internal memory)
6 x pclkp + 3 x mclkp 8 x pclkp + 9 x mclkp 12 x pclkp + 15 x mclkp ns
Writes to:
60h—93h,
A0h—D7h,
E0h—FFh
(direct internal memory)
6 x pclkp
8 x pclkp + 4 x mclkp 10 x pclkp + 9 x mclkp ns
Reads to Extended Memory 6 x pclkp + 6 x mclkp 8 x pclkp + 12 x mclkp 12 x pclkp + 18 x mclkp ns
Internal Structures
Writes to Extended Memory
Internal Structures
6 x pclkp
8 x pclkp + 7 x mclkp 10 x pclkp + 12 x mclkp ns
Read from LUT SRAM
4 x pclkp + 11 x mclkp
—
10 x pclkp + 50 x mclkp ns
Write to LUT SRAM
4 x pclkp
—
10 x pclkp + 50 x mclkp ns
Agere Systems Inc.
25