T8207 Datasheet, PDF (74/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
12 Traffic Management
12.1 Cell Loss Priority (CLP)
To avoid congestion, cells with their CLP bit set may be automatically discarded upon reception at the TX PHY
FIFO or upon reception at a queue in the SDRAM. The cells are discarded if the TX PHY FIFO or SDRAM queue is
filled beyond the programmed limit and this feature is enabled.
For the TX PHY FIFO, this limit is programmed in the clp_fill_limit bits of the main configuration/control register
(address 0110h). The feature is enabled when the cell_drop_en bit in the main configuration/control register
(address 0110h) is set.
For the SDRAM queues, this limit is programmed for each queue (X) in the clp_fillX[24:9] and clp_fillX[8:6] bits in
Table 119. The feature is enabled when the queueX_clp_en bit in the queue X registers (address 0440h through
04BEh) is set. When a received cell exceeds the CLP fill level for a queue, the T8207 sets the corresponding
queueX_clp_lim status bit in the queue X registers. If the fill level is set to zero, the corresponding queueX_clp_lim
bit is set by the first received cell for the queue. Any fill greater than zero has an inherent inaccuracy of seven cells;
therefore, a fill limit of eight or less is not meaningful. The number of cells in each queue may be determined by
reading the value of the read and write pointers for the specific queue.
12.2 Forward Explicit Congestion Notification (FECN)
The T8207 supports FECN for data cells using the explicit forward congestion indication (EFCI) bit in the cell
header PTI. If enabled, FECN indicates cells that have encountered congestion by setting their EFCI bit. The
T8207 sets the EFCI bit in cells that leave a queue that is filled beyond the limit programmed in the fecn_fillX[24:9]
and fecn_fillX[8:6] bits in Table 119. (See Figure 12.) The T8207 only sets the EFCI bit in cells when the function is
enabled by the queueX_fecn_en bit in the queue X registers (address 0440h through 04BEh). When a received
cell exceeds the FECN fill level for a queue, the T8207 sets the corresponding queueX_fecn_lim status bit in the
queue X registers. If the fill level is set to zero, the corresponding queueX_fecn_lim bit is set by the first received
cell for the queue. Any fill greater than zero has an inherent inaccuracy of seven cells; therefore, a fill limit of eight
or less is not meaningful. The number of cells in each queue may be determined by reading the value of the read
and write pointers for the specific queue.
12.3 Partial Packet Discard (PPD)
Partial packet discard (PPD) is accomplished through the cooperation of the T8207 (source) that places the cell on
the cell bus and the T8207 (destination) that receives the cell from the bus. The source T8207 uses its translation
RAM to place a unique ID (PPD pointer) and PPD enable bit in the cell for each AAL5 connection. The PPD pointer
and PPD enable bit may consist of any bit in the first 64 bits of the bus cell (cell bus routing header, tandem routing
header, and ATM cell header) and are created at connection establishment.
The destination T8207 uses the PPD state memory (address 1000h to 13FEh) to track the state of AAL5 virtual
channels for partial packet discard. Each bit in the memory represents one of 8192 potential AAL5 virtual channels.
When the virtual channel connection is initially established, the bit in PPD state memory pointed to by the PPD
pointer is cleared. When a cell that has its PPD enabled is discarded, the bit pointed to by the PPD pointer
becomes set. Once this bit is set, successive cells with the same PPD pointer will be discarded until the last cell is
received. The last cell is identified using the SDU-type bit in the PTI of the cell header. When the last cell of the
packet is received, the virtual channel’s corresponding bit in the PPD state memory is automatically cleared, and
the last cell is transmitted.
The ppd_en_sel[5:0] bits in the PPD information 1 register specify which of the bus cell’s first 64 bits (cell bus rout-
ing header, tandem routing header, and ATM cell header) enable PPD. PPD is enabled when the associated bit in
the headers is one. The partial packet discard bits specify which of the bus cell’s first 64 bits are used to create the
PPD pointer. These pointer bits are ppd_pnt0_sel[5:0] through ppd_pnt12_sel[5:0] in the PPD information 1
through 7 registers (addresses 0206h through 0212h). When an AAL5 virtual channel connection is initially estab-
lished, its PPD bit in the PPD state memory must be cleared using the write_pul, write_val, and write_addr bits in
the PPD memory write register at address 0418h.
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