T8207 Datasheet, PDF (65/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
11 SDRAM Interface (continued)
11.3 SDRAM Interface Timing
The mclk clock is the source of the SDRAM clock (sd_clk) from the T8207. Based on the frequency of the SDRAM
clock and the speed grade of the SDRAM, four timing parameters must be programmed into the SDRAM configu-
ration register at address 0408h. These timing parameters are specified in SDRAM (mclk) clock cycles and are
listed below:
s RAS inactive to CAS active (ras2cas)—its value may be set from two to four SDRAM clock cycles.
s CAS inactive to precharge command active (cas2pre)—its value may be set from one to four SDRAM clock
cycles.
s Precharge command inactive to next command active (pre2cmd)—its value may be set from one to four SDRAM
clock cycles.
s CAS before RAS (CBR) refresh command inactive to next CBR refresh command active (ref2cmd)—its value
may be set to 3, 7, or 15 SDRAM clock cycles.
Actual values for these parameters are obtained from the data sheet of the SDRAM used. For optimum perfor-
mance, these parameters should be programmed to the lowest acceptable values. The earliest time that a CAS
may be asserted after an RAS may be obtained from the data sheet parameter that describes the minimum time
from the activate command to the read/write command. Three parameters affect the earliest time that a precharge
command may follow a CAS. For read commands, a precharge command may be issued one clock earlier than the
last read data. The actual number of clock cycles depends on the CAS latency needed for the device. For write
commands, the earliest time that a precharge command may be issued following a CAS may be obtained from the
SDRAM data sheet parameter that describes the minimum time from the last data in to the precharge command. In
addition to these two parameters, the minimum time from the activate command to the precharge command may
need to be considered to obtain the value for cas2pre. If the SDRAM is only accessed for queuing purposes,
28 consecutive CAS commands will be executed between the activate command and the precharge command,
and the minimum time from the activate command to the precharge command does not need to be considered. If
the microprocessor reads and writes the SDRAM memory, only one CAS command will be executed between the
activate command and the precharge command. In this case, the minimum time from the activate command to the
precharge command is significant and must be considered. The minimum time from the precharge command to
the next command may be obtained from the data sheet parameter that describes the minimum time from the pre-
charge command to the activate command. The minimum time from the CBR refresh command to the next CBR
refresh command may be obtained from the data sheet. In the T8207, the minimum time from CBR refresh to any
other command is 15 SDRAM clock cycles. In the data sheet, the parameters may be specified in actual time units
rather than clock cycles. To determine the number of clock cycles, divide the parameter value by the SDRAM clock
period. Figure 18 below illustrates these timing parameters and the number of clock cycles needed to read or write
a cell using the default values for the parameters.
SINGLE COMMAND
RAS
(1)
CBR
REFRESH
(1)
ras2cas
{2, 3, 4}
CAS
(1 TO 28)
cas2pre
{1, 2, 3, 4}
PRECHARGE
(1)
pre2cmd
{1, 2, 3, 4}
ref2cmd
{3, 7, 15}
THE BOXES REPRESENT THE NUMBER
OF IDLE CYCLES BETWEEN STATES. DEFAULT
VALUES ARE IN BOLD FOR ras2cas, cas2pre, pre2cmd, AND ref2cmd.
NEXT
COMMAND
Agere Systems Inc.
Figure 18. SDRAM Timing Parameters
5-7785bF
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