T8207 Datasheet, PDF (23/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
6 Microprocessor Interface
6.1 Microprocessor Interface Configuration
The microprocessor interface may be configured for either Intel or Motorola mode via the mot_sel input. Tie
mot_sel high to select Motorola mode and low to select Intel mode. In addition, the address and data buses may
be configured for multiplexed or nonmultiplexed mode using the mux input. To select multiplexed mode, tie mux
high, and to select nonmultiplexed mode, tie mux low. In multiplexed mode, d[7:0] are used for both the address
and the data bus, and the a[0] input becomes an address latch enable (ale) signal. In nonmultiplexed mode, sepa-
rate address, a[7:0], and data, d[7:0], buses are used. In both modes, the active-low sel* input selects the device
for microprocessor read or write accesses. The data leads are 3-stated when the sel*, wr*_ds*, or rd*_wr* signal is
high.
In Motorola mode, rd*_rw* is a read/write enable signal, which indicates the current access is a read when it is high
and a write when low. The wr*_ds* signal is data strobe in Motorola mode. The rdy_dtack* output is an active-low
data transfer acknowledge signal. The T8207 takes this signal low when the microprocessor access is complete.
The rdy_dtack* output returns high when the microprocessor acknowledges the access by taking the sel* or
wr*_ds* signal high. The rdy_dtack* output then goes high-impedance.
In Intel mode, the rd*_rw* input is an active-low read enable signal, and wr*_ds* is an active-low write enable sig-
nal. A logic low level on rd*_rw* indicates to the T8207 that the current access is a read, and a logic low level on
wr*_ds* indicates the access is a write. Finally, the rdy_dtack* output is an active-high ready signal. The T8207
asserts this signal high when a microprocessor access is complete. The rdy_dtack* output then goes high-imped-
ance when the sel*, wr*_ds*, or rd*_wr* signal goes high.
6.2 Microprocessor Interrupts
The int_irq* output is an active-high interrupt in Intel mode and an active-low interrupt request in Motorola mode. In
Intel mode, int_irq* is normally low and goes high when an interrupt is generated. In Motorola mode, the interrupt
request signal is normally high and goes low during an interrupt. Interrupts are generated when an enabled inter-
rupt status bit becomes set. All interrupt status bits in the T8207 have a corresponding interrupt enable bit. When
the enable bit is cleared, the corresponding interrupt status bit is not enabled and will not generate an interrupt.
Several registers containing interrupt status bits exist in the three separate extended memory register groups
(main, UTOPIA, and SDRAM) of the T8207. The interrupt service request register at direct address 29h indicates
which register group is generating the interrupt. Only enabled interrupts will cause the int_serv_mainreg,
int_serv_sdramreg, and int_serv_utopiareg bits to become set. For the main register group, a special case exists.
The ctrl_cell_sent and the ctrl_cell_av interrupts (in the main interrupt status 1 register) do not cause the main
group indication bit to be set in the interrupt service request register. These interrupts have their own dedicated
service request bits to optimize sending and receiving control cells. The ctrl_cell_sent and ctrl_cell_av bits may
become set whether the corresponding interrupt is enabled or not.
6.3 Accessing the CelXpres T8207 via Microprocessor Interface
The CelXpres T8207 has two distinct memory spaces, the direct memory access registers and the extended mem-
ory registers. The direct memory access registers are directly addressed 8-bit (byte) registers and are mapped
between addresses 00h and FFh. The extended memory registers are indirectly addressed and mapped between
addresses 0100h and 3FFFFFEh. The extended memory contains the SDRAM memory, the translation RAM,
internal memories, and the device’s configuration, status, and control registers. Extended memory registers are
16 bits wide, and all accesses to the extended memory registers are executed internally as 16 bits. Direct memory
access registers are located in Section 14.2, Direct Memory Access Registers, and extended memory registers are
located in Section 14.3, Extended Memory Registers.
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