T8207 Datasheet, PDF (128/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
14 Registers (continued)
14.3.3 SDRAM Registers
Table 104. SDRAM Control (SCT) (0400h)
Name
sdram_en
gen_man_acc
Reserved
Reserved
Bit Pos.
0
1
14:2
15
Type
RW
WO
RO
RW
Reset
Description
0 SDRAM Enable. If this bit is set to ‘1,’ the SDRAM becomes
active. If ‘0,’ the SDRAM is in the idle state.
0 Generate Manual Access. If the sdram_en bit is ‘0,’ writing a ‘1’
to this bit will take the SDRAM out of its idle state and activate the
manual values programmed in the cas_man, ras_man, we_man,
bs_man, and addr_man bits. The ‘1’ pulses for one clock cycle
and clears to ‘0’ automatically. The SDRAM then returns to its
idle state. This special mode is used in the start-up sequence for
the SDRAM.
0 Reserved.
0 Reserved. Program this bit to ‘0.’
Table 105. SDRAM Interrupt Status (SIS) (0402h)
Name
ref_late
crc8_err_even
crc8_err_odd
Reserved
Bit Pos.
0
1
2
15:3
Type
ROL
ROL
ROL
RO
Reset
Description
0 Refresh Late. This bit is set when the refresh cycle for the
SDRAM is greater than the value programmed in the late_lim
bits. An interrupt is generated if the corresponding enable bit is
set.
0 CRC-8 Error on Even Data Byte. This bit is set when an error is
detected on the even byte (sd_d[15:8]) of the SDRAM data bus.
An interrupt is generated if the corresponding enable bit is set.
0 CRC-8 Error on Odd Data Byte. This bit is set when an error is
detected on the odd byte (sd_d[7:0]) of the SDRAM data bus. An
interrupt is generated if the corresponding enable bit is set.
0 Reserved.
Table 106. SDRAM Interrupt Enable (SIE) (0404h)
Name
ref_late_ie
crc8_err_even_ie
crc8_err_odd_ie
Reserved
Bit Pos.
0
1
2
15:3
Type
RW
RW
RW
RO
Reset
Description
0 Refresh Late Interrupt Enable. An interrupt is generated if this
bit and the corresponding status bit are set. The interrupt is gen-
erated until this bit or the corresponding status bit is reset.
0 CRC-8 Error on Even Data Byte Interrupt Enable. An interrupt
is generated if this bit and the corresponding status bit are set.
The interrupt is generated until this bit or the corresponding sta-
tus bit is reset.
0 CRC-8 Error on Odd Data Byte Interrupt Enable. An interrupt
is generated if this bit and the corresponding status bit are set.
The interrupt is generated until this bit or the corresponding sta-
tus bit is reset.
0 Reserved.
128
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