T8207 Datasheet, PDF (132/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
14 Registers (continued)
Table 114. SDRAM Interrupt Service Request 4 (SISR4) (0438h)
Name
queue_serv[63:48]
Bit Pos. Type
15:0 RO
Reset
Description
0 Queue Service [63:48]. Each bit in this field represents one of
16 queue X registers from the 64 queue X registers. The least
significant bit represents the queue 48 register. The most sig-
nificant bit represents the queue 63 register. If the correspond-
ing bit is ‘1,’ the specific queue X register has interrupt status
bits that need servicing (see Table 118).
Table 115. SDRAM Interrupt Service Request 3 (SISR3) (043Ah)
Name
queue_serv[47:32]
Bit Pos. Type
15:0 RO
Reset
Description
0 Queue Service [47:32]. Each bit in this field represents one of
16 queue X registers from the 64 queue X registers. The least
significant bit represents the queue 32 register. The most sig-
nificant bit represents the queue 47 register. If the correspond-
ing bit is ‘1,’ the specific queue X register has interrupt status
bits that need servicing (see Table 118).
Table 116. SDRAM Interrupt Service Request 1 (SISR1) (043Ch)
Name
queue_serv[31:16]
Bit Pos. Type
15:0 RO
Reset
Description
0 Queue Service [31:16]. Each bit in this field represents one of
16 queue X registers from the 64 queue X registers. The least
significant bit represents the queue 16 register. The most sig-
nificant bit represents the queue 31 register. If the correspond-
ing bit is ‘1,’ the specific queue X register has interrupt status
bits that need servicing (see Table 118).
Table 117. SDRAM Interrupt Service Request 2 (SISR2) (043Eh)
Name
queue_serv[15:0]
Bit Pos.
15:0
Type
RO
Reset
Description
0 Queue Service [15:0]. Each bit in this field represents one of
16 queue X registers from the 64 queue X registers. The least
significant bit represents the queue 0 register. The most signif-
icant bit represents the queue 15 register. If the corresponding
bit is ‘1,’ the specific queue X register has interrupt status bits
that need servicing (see Table 118).
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