T8207 Datasheet, PDF (134/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
14 Registers (continued)
Table 118. Queue X (QX) (0440h to 04BEh) (continued)
Name
Bit Pos.
Type
Reset
Description
queueX_emp_ie 15
RW
0 Queue X Empty Interrupt Enable. An interrupt is
generated if this bit and the corresponding status bit
are set. The interrupt is generated until this bit or the
corresponding status bit is reset.
The letter X in the register name and in the bit names represents the values of 0 through 63 for the 64 queues
shown below.
Register
Name
Queue 0 (Q0)
Queue 1 (Q1)
Queue 2 (Q2)
Queue 3 (Q3)
Queue 4 (Q4)
Queue 5 (Q5)
Queue 6 (Q6)
Queue 7 (Q7)
Queue 8 (Q8)
Queue 9 (Q9)
Queue 10 (Q10)
Queue 11 (Q11)
Queue 12 (Q12)
Queue 13 (Q13)
Queue 14 (Q14)
Queue 15 (Q15)
Register
Address
0440h
0442h
0444h
0446h
0448h
044Ah
044Ch
044Eh
0450h
0452h
0454h
0456h
0458h
045Ah
045Ch
045Eh
Register
Name
Queue 16 (Q16)
Queue 17 (Q17)
Queue 18 (Q18)
Queue 19 (Q19)
Queue 20 (Q20)
Queue 21 (Q21)
Queue 22 (Q22)
Queue 23 (Q23)
Queue 24 (Q24)
Queue 25 (Q25)
Queue 26 (Q26)
Queue 27 (Q27)
Queue 28 (Q28)
Queue 29 (Q29)
Queue 30 (Q30)
Queue 31 (Q31)
Register
Address
Register
Name
0460h Queue 32 (Q32)
0462h Queue 33 (Q33)
0464h Queue 34 (Q34)
0466h Queue 35 (Q35)
0468h Queue 36 (Q36)
046Ah Queue 37 (Q37)
046Ch Queue 38 (Q38)
046Eh Queue 39 (Q39)
0470h Queue 40 (Q40)
0472h Queue 41 (Q41)
0474h Queue 42 (Q42)
0476h Queue 43 (Q43)
0478h Queue 44 (Q44)
047Ah Queue 45 (Q45)
047Ch Queue 46 (Q46)
047Eh Queue 47 (Q47)
Register
Address
0480h
0482h
0484h
0486h
0488h
048Ah
048Ch
048Eh
0490h
0492h
0494h
0496h
0498h
049Ah
049Ch
049Eh
Register
Name
Queue 48 (Q48)
Queue 49 (Q49)
Queue 50 (Q50)
Queue 51 (Q51)
Queue 52 (Q52)
Queue 53 (Q53)
Queue 54 (Q54)
Queue 55 (Q55)
Queue 56 (Q56)
Queue 57 (Q57)
Queue 58 (Q58)
Queue 59 (Q59)
Queue 60 (Q60)
Queue 61 (Q61)
Queue 62 (Q62)
Queue 63 (Q63)
Register
Address
04A0h
04A2h
04A4h
04A6h
04A8h
04AAh
04ACh
04AEh
04B0h
04B2h
04B4h
04B6h
04B8h
04BAh
04BCh
04BEh
Note: When the T8207_sel bit = 0, queues 32—63 are disabled (default).
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Agere Systems Inc.