T8207 Datasheet, PDF (18/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
2 Pin Description (continued)
Table 7. General-Purpose Pins
Symbol
gpio[7:0]
reset*
xtalin
xtalout
cko
cko_e
NC
Ball
U5, Y3, Y4, V5,
W5, Y5, V6, U7
V14
V13
Y14
W11
V11
A2, A3, A16, B2,
B3, B4, C3, C4,
C5, D5, U16, V3,
V4, V17, V18,
W1, W2, W3,
W4, W18, W19,
Y1, Y2, Y15,
Y17, Y18, Y19,
Y20
Reset
Value
—
—
—
—
—
—
—
Type
Name/Description
I/O General-Purpose I/O. 4 mA drive, TTL compatible I/O, 5 V
tolerant.
I Reset (Active-Low). Schmitt trigger, TTL compatible input,
5 V tolerant.
I Crystal Input (pclk). This input may be driven by either a
crystal or an external clock. If a crystal is used, connect it
between this pin and xtalout and connect the appropriately
valued capacitor from this pin to VSS.
If an external clock is used, this is a 5 V tolerant CMOS
input with 50 MHz max input frequency.
O Crystal Output Feedback. If a crystal is used, connect it
between this pin and xtalin and connect the appropriately
valued capacitor from this pin to VSS. If an external clock is
used to drive xtalin, this pin must be left unconnected.
O Buffered Clock Output. If enabled, pclk is output on this
pin. 8 mA drive, TTL compatible output. This pin is high
impedance if not enabled.
I CKO Enable. Enable for buffered clock output. If cko is not
used, tie this enable pin low. Active-high, TTL compatible
input, 5 V tolerant.
— No Connection. Reserved.
Table 8. Power Pins
Symbol
VDD
VSS
VDDA
Ball
D6, D11, D15, F4, F17, K4, L17, R4, R17, U6,
U10, U15
A1, D4, D8, D13, D17, H4, H17, J9, J10, J11,
J12, K9, K10, K11, K12, L9, L10, L11, L12, M9,
M10, M11, M12, N4, N17, U4, U8, U13, U17
W14
Name/Description
Power. 3.3 V. These pins should be properly
decoupled using 0.01 µF or 0.1 µF capacitors.
Ground.
Clock Oscillator Power. 3.3 V. This pin should
be properly decoupled using 0.01 µF or 0.1 µF
capacitors.
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