T8207 Datasheet, PDF (60/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
10 Cell Bus Interface (continued)
10.3.2 Data Cells
Data cells accepted from the cell bus are routed to the TX PHY FIFO. From the TX PHY FIFO, the cell is routed to
the appropriate transmit queue using the information about the cell’s priority and the queue group to which it is des-
tined. The priority of the cell is indicated by 2 bits obtained from the first 64 bits of the bus cell (cell bus routing
header, tandem routing header, and ATM cell header). The position of these 2 bits in the cell are user programma-
ble during configuration using the prior0_sel[5:0] and prior1_sel[5:0] bits of the routing information 3 register
(address 0204h). The queue group to which the cell is destined is indicated by 4 bits obtained from the first 64 bits
of the bus cell (cell bus routing header, tandem routing header, and ATM cell header). The position of these 4 bits
in these headers are user programmable using the mphy1_sel[5:0] and mphy2_sel[5:0] bits of the routing informa-
tion 1 register (address 0200h) and the mphy3_sel[5:0] and mphy0_sel[5:0] bits of the routing information 2 regis-
ter (address 0202h). See Tables 90, 91, and 92 in Section 14.3, Extended Memory Registers. None of the priority
or MPHY bits are required to be adjacent. For more information on queue groups, see Section 11.4, Queuing.
If the T8207_sel bit (Table 59) is zero, the mphy3_sel[5:0] bits are not used.
10.3.3 Loopback Cells
A loopback cell may be sent to the cell bus for diagnostic purposes. Initially, the loopback cell is sent from one
T8207 (device 1) to a second T8207 (device 2). The second T8207 (device 2) returns the cell to the first T8207
(device 1), or, if desired, the second T8207 (device 2) may send the cell on to one or more entirely different T8207
devices. Device 2 accepts the loopback cell and replaces the most significant 12 bits of the cell bus routing header
with the routing_header bits in its loopback register (address 0118h). The 12 routing_header bits in the loopback
register correspond to the upper 12 bits of a single destination control cell header, a multicast control cell header, or
a broadcast control cell header. (See Figure 16.)
To create a loopback path from device 1 to device 2, and back to device 1, coordinated control of device 1 and
device 2 is needed. First, the microprocessor connected to device 2 sets up the loopback by writing the
routing_header bits in the loopback register of device 2. The routing_header bits indicate a single destination con-
trol cell with a unit address field for device 1. Second, the microprocessor connected to device 1 writes a loopback
cell to the control cell transmit direct memory (addresses A0h to D7h) of device 1. (See Section 10.3.1, Control
Cells of this document.) The cell bus routing header of this cell is the single destination loopback type, and the unit
address section of the header contains the address of device 2. To send the loopback cell, a ‘1’ is then written to
the cntl_cell_wr bit of the main configuration/control register (address 0110h).
Care must be taken to ensure that the routing_header bits in a T8207 device are not changed until any previously
setup loopback cell has been received and retransmitted. If these bits are changed prematurely, misrouting will
occur.
10.3.4 Multicast Routing
The T8207 may be programmed to accept certain multicast data cells using the multicast memories at addresses
E0h through FFh (or 0C00h through 0C1Eh) and 0C20h through 0DFEh. The net numbers of accepted multicast
control cells are programmed in the memory space E0h through FFh (or 0C00h through 0C1Eh) and 0C20h
through 0DFEh. These memory spaces hold 256 bits each. Each bit represents a multicast net number from 0 to
255.
If the T8207_sel bit (Table 59) is cleared, the multicast memories at addresses 0D00h to 0DFEh are ignored.
Note: To prevent potential multicast memory errors, these memory spaces should be cleared during the initializa-
tion process.
For ATM mode, if the T8207_sel bit is cleared, the net numbers of accepted multicast data cells are programmed in
the multicast number memories, which are divided among eight PHY ports. If 16 ports are used in this mode, each
memory space is shared between two ports, e.g., ports zero and one use the memory assigned to PHY 0, ports two
and three use the memory assigned to PHY 1, and so on (see Section 9.2.2, Outgoing ATM Mode (Cells Sent by
T8207)).
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