T8207 Datasheet, PDF (79/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
14 Registers
The T8207 has two distinct memory spaces, which are the direct memory access registers and the extended mem-
ory registers. The direct memory access registers are directly addressed 8-bit (byte) registers and are mapped
between addresses 00h and FFh. The extended memory registers are indirectly addressed and mapped between
addresses 0100h and 3FFFFFEh. The extended memory registers are mapped into three major blocks: the main
registers, the UTOPIA registers, and the SDRAM registers. They contain the SDRAM memory, the translation
RAM, internal memories, and the device’s configuration, status, and control registers. Extended memory registers
are 16 bits wide. All accesses to the extended memory registers are executed internally as 16 bits. Direct memory
access registers are located in Section 14.2, Direct Memory Access Registers, and extended memory registers are
located in Section 14.3, Extended Memory Registers.
14.1 Register Types
Read/Write (RW):
Read Only (RO):
Read-Only Latch (ROL):
Write Only (WO):
These registers may be written or read.
These registers may only be read.
The read-only latch is used for interrupt status registers. Reading a read-only latch
register has no effect on the contents. To clear a bit set in an ROL register, a one
must be written to the bit. Writing a zero to the bit has no effect. If the corresponding
interrupt enable bit is set, an interrupt will be continuously generated until the bit in
the ROL register is cleared.
These registers may only be written. The write-only registers in the T8207 are a
pulse type. When they are written to one, they generate a pulse internally for one
clock cycle and then return to zero.
Table 23. Register Map
Register Name
Direct Configuration/Control Register (DCCR)
Interrupt Service Request (ISREQ)
mclk PLL Configuration 0 (MPLLCF0)
mclk PLL Configuration 1 (MPLLCF1)
GTL+ Slew Rate Configuration (GTLSRCF)
GTL+ Control (GTLCNTRL)
Extended Memory Address 1 (Little Endian) (EMA1_LE)
Extended Memory Address 2 (Little Endian) (EMA2_LE)
Extended Memory Address 3 (Little Endian) (EMA3_LE)
Extended Memory Address 4 (Little Endian) (EMA4_LE)
Extended Memory Access (Little Endian) (EMA_LE)
Extended Memory Data Low (Little Endian) (EMDL_LE)
Extended Memory Data High (Little Endian) (EMDH_LE)
Extended Memory Address 4 (Big Endian) (EMA4_BE)
Extended Memory Address 3 (Big Endian) (EMA3_BE)
Extended Memory Address 2 (Big Endian) (EMA2_BE)
Extended Memory Address 1 (Big Endian) (EMA1_BE)
Extended Memory Access (Big Endian) (EMA_BE)
Extended Memory Data High (Big Endian) (EMDH_BE)
Extended Memory Data Low (Big Endian) (EMDL_BE)
GPIO Output Enable (GPIO_OE)
GPIO Output Value (GPIO_OV)
Address (h)
28h
29h
2Ah
2Bh
2Eh
2Fh
30h
31h
32h
33h
34h
36h
37h
30h
31h
32h
33h
34h
36h
37h
39h
3Bh
Reference Page
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