T8207 Datasheet, PDF (61/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
10 Cell Bus Interface (continued)
10.3.4 Multicast Routing (continued)
For ATM mode, if the T8207_sel bit is set, the net numbers of accepted multicast data cells are programmed in the
multicast number memories, which are divided among sixteen PHY ports. If 16 ports are used, each port has one
memory space. If 32 ports are used, each memory space is shared between two ports, e.g., ports zero and one
use the memory assigned to PHY 0, ports two and three use the memory assigned to PHY 1, and so on.
The cell priority bits select the specific queue in the queue group to which the cell is routed. (See Section 11.4,
Queuing.) Note that multicast control cells use the same multicast number memory as PHY 0 multicast data cells.
See Table 122 in Section 14.3, Extended Memory Registers and Table 52 in Section 14.2, Direct Memory Access
Registers, respectively.
For PHY mode, multicast cells are only transmitted to queue group 0, and only the PHY port 0 and control cell mul-
ticast direct memory at addresses E0h through FFh (or 0C00h through 0C1Eh) is used. The cell priority determines
the specific queue in queue group 0 to which the cell is routed. (See Section 10.3.2, Data Cells.)
10.3.5 Broadcast Routing
Broadcast control cells are transmitted and received as described in Section 10.3.1, Control Cells. The broadcast
control cell bus routing header has a broadcast control cell header type.
For ATM mode, if the T8207_sel bit (Table 59) is cleared and 8 PHY ports or less are being used, the broadcast
data cells are transmitted to all the ports. If 16 ports are used, the broadcast data cells are transmitted to only 8 of
the 16 ports depending on the cell priority bits that select the specific queue.
For ATM mode, if the T8207_sel bit (Table 59) is set, and 16 PHY ports or less are being used, the broadcast data
cells are transmitted to all the ports. If 32 ports are used, the broadcast data cells are transmitted to only 16 of the
32 ports depending on the cell priority bits that select the specific queue.
For PHY mode, if SDRAM is bypassed, broadcast data cells are only transmitted to queue 0. If the SDRAM is not
bypassed, broadcast data cells are only transmitted to queue group 0, and only PHY port 0 is used (although the
device will take the time to try to broadcast data cells to all the ports, cells will not be stored in queue groups other
than 0).
10.4 Cell Bus Arbitration
One of the T8207 devices sharing the cell bus must be configured as bus arbiter by clearing the cb_arb_sel bit in
the cell bus configuration/status register (address 0130h) or by pulling the arb_en* lead low. Using an arbitration
algorithm, the arbiter decides the next device to transmit on the cell bus and issues the grant signals at the end
of the cell bus frame. The arbiter also generates the active-low frame synchronization signal that occurs every
16 clock cycles in 16-user mode and every 32 clock cycles in 32-user mode.
To grant transmission requests, the arbiter must analyze requests received during the request section of the cur-
rent frame for 16-user mode or during two request cycles for 32-user mode. The arbitration algorithm used is
round-robin and based on the priority of the request and the last request granted.
The arbiter circuitry in all T8207 devices on the cell bus will synchronize to the active arbiter on the cell bus. So,
when an inactive device becomes the arbiter, it will begin sending frame synchronization signals that coincide to
the clock cycle that the original arbiter would have sent its next frame synchronization signal. This prevents the
new arbiter from misinterpreting random signals on its first request cycle as valid requests.
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