T8207 Datasheet, PDF (72/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
11 SDRAM Interface (continued)
Of the four priority queues, the highest-priority (priority zero), lowest-delay queue may be used for constant bit rate
(CBR) traffic. The other three queues, in descending order of priority, may be used for variable bit rate (VBR), avail-
able bit rate (ABR), and unspecified bit rate (UBR) traffic, respectively. Generally, as the priority becomes lower, the
queues become larger because lower-priority cells are likely to accumulate while higher-priority cells are transmit-
ted.
The size and location of each queue is programmable using the base_addressX[24:6] and end_addrX[24:6] bits in
the Queue X Definition Structure shown in Table 119. Using these base and end address registers, the size of each
queue may be programmed to a minimum of four cells and up to a maximum of 512K cells in one-cell increments.
Each queue must be disabled during queue configuration by clearing the queueX_rd_en and queueX_wr_en bits in
the queue X registers (addresses 0440h through 04BEh) (Table 118).
Cells sent to write-disabled queues will be discarded. Cells sent to read-disabled queues will be written into the
SDRAM but never transmitted to the TX UTOPIA port. Read-disabled queues may be used, as large external
memory, to store cells bound for the microprocessor. The microprocessor may use as many queues as required for
different type cells. Because the microprocessor reads only 2 bytes from the SDRAM per access, the cas2pre
value (see Section 11.3, SDRAM Interface Timing) may need to be larger than that required for the transferring of
cells only. Therefore, to maximize the bandwidth of the SDRAM for cell bus to UTOPIA traffic, restrict microproces-
sor access of the SDRAM to the initialization function (e.g., downloading microcode over the cell bus).
When the microprocessor increments the read pointer to read the SDRAM, it must first write the three least signifi-
cant bits (rd_pntX[8:6]) of the read pointer for the appropriate queue followed by the 16 most significant bits
(rd_pntX[24:9]). This order must be followed for proper operation. All queues used for microprocessor cell recep-
tion must be at least 32 cells long. (See the Queue X Definition Structure, Table 119, for more information on these
bits.)
11.5 SDRAM Refresh
The T8207 SDRAM interface performs CAS before RAS (CBR) refresh commands at a rate programmed in the
ref_cnt bits of the refresh register (address 0410h). The value in the refresh register represents refresh cycles in
SDRAM clock cycles. One refresh command is executed every ref_cnt clock cycles, on average, when the SDRAM
is idle. In addition, the value programmed in the refresh lateness register (address 0412h) represents the maximum
time, in programmed refresh cycles, between actual refresh cycles. If this limit is exceeded, the ref_late bit in the
SDRAM interrupt status register (address 0402h) will be set, and if the ref_late interrupt is enabled, an interrupt will
be generated. The ref_late indication is provided for diagnostic purposes and does not necessarily indicate a fatal
error. Bit errors in the actual cell are reported in the crc8_err_even and crc8_err_odd bits of the SDRAM interrupt
status register.
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