T8207 Datasheet, PDF (66/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
11 SDRAM Interface (continued)
11.4 Queuing
Queuing is different for a T8207 device with its T8207_sel (Table 59) bit set than a T8207 device with its T8207_sel
bit cleared.
For a device configured in ATM mode with its T8207_sel bit set, up to 16 groups of queues with four priorities per
group may be configured in the SDRAM for a total of 64 queues. Therefore, the four port group address bits point
to one of 16 queue groups, and the two priority bits point to one of four queues in the group. (For a description of
the port group address and priority bits, see Section 10.3.2, Data Cells.) Priority bits with a value of zero represent
the highest priority, and those with a value of three, the lowest priority.
If the ATM is configured to support eight or less PHY ports, each port is mapped to one queue group using the
port_rte[31:0] bits in the TX PHY FIFO routing 0 and 1 registers (addresses 017Ch and 017Eh). For example, for a
configuration of eight PHY ports, which includes ports 0, 2, 4, 6, 8, 10, 12, and 14, PHY port 0 is assigned queue
group zero or queues zero, one, two, and three. Likewise, PHY port 2 is assigned group one or queues four, five,
six, and seven, and so on.
An ATM configured to support 16 PHY ports is a special case. When the T8207_sel bit is set and the ATM is con-
figured to support 16 PHY ports, each port (0—15) is assigned to its associated queue group as illustrated in Table
18, regardless of the value of the port_rte[63:0] bits. In this case, port 0 is assigned to queue group 0, port 1 to
queue group 1, and so on.
For an ATM configured to support 32 PHY ports, each queue group is shared between two ports as specified in
Section 9.2.2, Outgoing ATM Mode (Cells Sent by T8207), and the four queues may be split in any way between
the two ports using the port_rte[63:0] bits. Table 19 illustrates the relationship between the queue organization and
the port group address/priority bits for a device configured to support 32 PHY ports and whose port_rte[63:0] bits
are programmed to the normal 32-port mode as described in Section 9.2.2, Outgoing ATM Mode (Cells Sent by
T8207). See the TX PHY FIFO routing 3, 2, 0, and 1 registers at addresses 0178h, 017Ah, 017Ch, and 017Eh.
When the T8207_sel bit is cleared, 32 PHY ports are not supported. In this mode, eight or less PHY ports are each
mapped to one queue group using the port_rte[31:0] bits in the TX PHY FIFO routing 0 and 1 registers. For 16 PHY
ports, each queue group is shared between two ports, and the four queues may be split in any way between the
two ports using the port_rte[31:0] bits. Table 20 illustrates the relationship between the queue organization and the
port address/priority bits for a device configured to support 16 PHY ports and whose port_rte[31:0] bits are pro-
grammed to the normal 16-port mode as described in Section 9.2.2, Outgoing ATM Mode (Cells Sent by T8207).
See the TX PHY FIFO routing 0 and 1 registers at addresses 017Ch and 017Eh.
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