T8207 Datasheet, PDF (130/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
14 Registers (continued)
Table 108. Refresh (RFRSH) (0410h)
Name
ref_cnt
Bit Pos.
15:0
Type
RW
Reset
Description
0400h Refresh Count. These bits are used to program the refresh cycle in
SDRAM clock cycles. The number of clock cycles programmed in
this register should be less than one half the worst-case refresh
period.
Table 109. Refresh Lateness (RFRSHL) (0412h)
Name
late_lim
Bit Pos.
15:0
Type
RW
Reset
Description
0400h Lateness Limit. These bits are used to program how late a refresh
cycle may occur. This limit is in refresh cycles. When this limit is
reached, the ref_late status bit will be set.
Table 110. Idle State 1 (IS1) (0420h)
Name
cas_idle
ras_idle
we_idle
bs_idle[1:0]
Reserved
Bit Pos.
0
1
2
4:3
15:5
Type
RW
RW
RW
RW
RO
Reset
Description
1 SDRAM CAS Idle Value. This is the value that will be placed on the
sd_cas* pin while the SDRAM is idle (sdram_en = ‘0’).
1 SDRAM RAS Idle Value. This is the value that will be placed on the
sd_ras* pin while the SDRAM is idle (sdram_en = ‘0’).
1 SDRAM Write Enable Idle Value. This is the value that will be
placed on the sd_we* pin while the SDRAM is idle (sdram_en = ‘0’).
3h SDRAM Bank Select Idle Value. This is the value that will be
placed on the sd_bs[1:0] pins while the SDRAM is idle
(sdram_en = ‘0’).
0 Reserved.
Table 111. Idle State 2 (IS2) (0422h)
Name
addr_idle[11:0]
Reserved
Bit Pos.
11:0
15:12
Type
RW
RO
Reset
Description
0 SDRAM Address Idle Value. This is the value that will be placed on
the sd_a[11:0] pins while the SDRAM is idle (sdram_en = ‘0’).
0 Reserved.
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