T8207 Datasheet, PDF (150/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
19 Timing Requirements (continued)
WRITE_ACCESS_ACTIVE¹
t1
t2
t3
t4
t5
t6
t11
A[0]/ALE
D[7:0]
t10
RDY_DTACK*²
t7
t8
t9
1. write_access_active is the logical OR function of sel* and wr*_ds*.
2. Load is 50 pF.
Note: sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active signal.
5-7791bF
Figure 25. Multiplexed Intel Mode Write Access Timing
READ_ACCESS_ACTIVE¹
t1
t2
t3
t4
t5
t6
t12
A[0]/ALE
D[7:0]
RDY_DTACK*²
t10
t11
t7
t8
t9
1. read_access_active is the logical OR function of sel* and rd*_wr*.
2. Load is 50 pF.
Note: sel* and rd*_wr* must not have coinciding edges in opposite directions prevent glitches on the read_access_active signals.
5-7792bF
Figure 26. Multiplexed Intel Mode Read Access Timing
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Agere Systems Inc.