T8207 Datasheet, PDF (104/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
14 Registers (continued)
Table 69. Main Interrupt Enable 2 (MIE2) (0134h)
Name
lb_cell_lost_ie
Reserved
cb_in_fifo_ovrn_ie
tx_phy_fifo_ovrn_ie
cell_clp1_dis_ie
rx_utopia_fifo_ovrn_ie
cntl_cell_rx_fifo_ovrn_ie
Reserved
Bit Pos.
0
1
2
3
4
5
6
15:7
Type Reset
Description
RW 0 Loopback Cell Lost Interrupt Enable. An interrupt is
generated if this bit and the corresponding status bit are
set. The interrupt is generated until this bit or the corre-
sponding status bit is reset.
RW 0 Reserved. Program this bit to zero.
RW 0 Cell Bus Input FIFO Overrun Interrupt Enable. An inter-
rupt is generated if this bit and the corresponding status bit
are set. The interrupt is generated until this bit or the corre-
sponding status bit is reset.
RW 0 TX PHY FIFO Overrun Interrupt Enable. An interrupt is
generated if this bit and the corresponding status bit are
set. The interrupt is generated until this bit or the corre-
sponding status bit is reset.
RW 0 Cell with CLP Set to One Discarded Interrupt Enable.
An interrupt is generated if this bit and the corresponding
status bit are set. The interrupt is generated until this bit or
the corresponding status bit is reset.
RW 0 RX UTOPIA FIFO Overrun Interrupt Enable. An interrupt
is generated if this bit and the corresponding status bit are
set. The interrupt is generated until this bit or the corre-
sponding status bit is reset.
RW 0 Control Cell RX FIFO Overrun Interrupt Enable. An
interrupt is generated if this bit and the corresponding sta-
tus bit are set. The interrupt is generated until this bit or the
corresponding status bit is reset.
RO 0 Reserved.
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