T8207 Datasheet, PDF (151/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
19 Timing Requirements (continued)
Table 139. Multiplexed Intel Mode Write Access Timing
Symbol
Parameter
Min
t1 a[0]/ale High Pulse Width
5
t2 write_access_active Falling Edge to a[0]/ale Falling Edge —
t3 d[7:0] Valid to a[0]/ale Falling Edge
5
t4 a[0]/ale Falling Edge to d[7:0] Invalid
0
t5 rdy_dtack* Rising Edge to write_access_active Rising
0
Edge
t6 rdy_dtack* Rising Edge to d[7:0] Invalid and a[0]/ale Ris-
0
ing Edge
t7 write_access_active Falling Edge to rdy_dtack* Falling
0
Edge
t8 rdy_dtack* Low Pulse Width¹
—
t9 write_access_active Rising Edge to rdy_dtack* 3-state
0
t10 write_access_active Falling Edge to d[7:0] Valid
—
t11 write_access_active Rising Edge to write_access_active 25
Falling Edge
1. See access times in Table 10.
Note: The term pclkp in the table represents the period of pclk in ns.
Typ
Max
Unit
—
—
ns
— 2 x pclkp – 4 ns
—
—
ns
—
—
ns
—
—
ns
—
—
ns
—
12
ns
—
—
—
—
5
ns
— 2 x pclkp – 4 ns
—
—
ns
Table 140. Multiplexed Intel Mode Read Access Timing
Symbol
Parameter
Min
Typ
Max
Unit
t1 a[0]/ale High Pulse Width
5
—
—
ns
t2 read_access_active Falling Edge to a[0]/ale Falling Edge
—
— 2 x pclkp – 4 ns
t3 d[7:0] Valid to a[0]/ale Falling Edge
5
—
—
ns
t4 a[0]/ale Falling Edge to d[7:0] Invalid
0
—
—
ns
t5 rdy_dtack* Rising Edge to read_access_active Rising
Edge
0
—
—
ns
t6 rdy_dtack* Rising Edge to a[0]/ale Rising Edge
0
—
—
ns
t7 read_access_active Falling Edge to rdy_dtack* Falling
0
—
12
ns
Edge
t8 rdy_dtack* Low Pulse Width¹
—
—
—
—
t9 read_access_active Rising Edge to d[7:0] Invalid and
rdy_dtack* 3-state
0
—
5
ns
t10 read_access_active Falling Edge to d[7:0] Drive
3 x pclkp – 4 —
—
ns
t11 d[7:0] Valid to rdy_dtack* Rising Edge
pclkp – 4
—
—
ns
t12 read_access_active Rising Edge to read_access_active
25
—
—
ns
Falling Edge
1. See access times in Table 10.
Note: The term pclkp in the table represents the period of pclk in ns.
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