T8207 Datasheet, PDF (85/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
14 Registers (continued)
Table 30. mclk PLL Configuration 1 (MPLLCF1) (2Bh)
Name
pll_m[4:0]
pll_n[2:0]
Bit Pos.
4:0
7:5
Type
RW
RW
Reset
Description
0 PLL M Count Value. See Section 5, PLL Configuration, for informa-
tion on these bits.
0 PLL N Count Value. See Section 5, PLL Configuration, for informa-
tion on these bits.
Table 31. GTL+ Slew Rate Configuration (GTLSRCF) (2Eh)
Name
slew_rate[2:0]
Bit Pos.
2:0
Type
RW
Reset
Description
4h GTL+ Slew Rate Control [2:0]. The slew rates of the GTL+ (cell bus)
output signals are controlled by these bits. The minimum slew rate
time is 0.9 ns and the maximum slew rate time is 3.8 ns.
Reserved
Reserved
“000” = Fastest slew rate
“001”
“010”
“011” = Nominal slew rate (on fast side)
“100” = Nominal slew rate (on slow side)
“101”
“110”
“111” = Slowest slew rate
3
RW 1 Reserved. Program to ‘1.’
7:4 RW 0 Reserved. Program to ‘0.’
Table 32. GTL+ Control (GTLCNTRL) (2Fh)
Name
Reserved
GTLRPDN
GTLTPDN
Reserved
Reserved
Reserved
Bit Pos. Type Reset
Description
0
R
1 Reserved. Program to ‘1.’
1
RW 1 GTL+ Receive Powerdown. When this bit is cleared to ‘0,’ the
GTL+ receivers on the cell bus pins are powered down. Under
this condition, no cells can be received from the backplane.
When this bit is set to ‘1,’ the GTL+ receivers are powered up
and cells are received from the backplane.
2
RW 1 GTL+ Transmit Powerdown. When this bit is cleared to ‘0,’
the GTL+ transmitters on the cell bus pins are powered down.
Under this condition, no cells can be transmitted to the back-
plane.
When this bit is set to ‘1,’ the GTL+ transmitters are powered
up and cells are transmitted to the backplane.
4:3
R
0 Reserved. Program to ‘0.’
5
R
1 Reserved. Program to ‘1.’
7:6
R
0 Reserved. Program to ‘0.’
Agere Systems Inc.
85