T8207 Datasheet, PDF (89/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
14 Registers (continued)
Table 44. Extended Memory Access (Big Endian) (EMA_BE) (34h)
Name Bit Pos.
ext_a[5:1] 4:0
ext_we[1:0] 6:5
ext_strt_acc 7
Type
RW
RW
RW
Reset
Description
0 Extended Access Address [5:1]. This extended access register points
to words. ext_a[0] is hardwired to ‘0.’
0 Extended Access Write Enable. These bits are active-high write
enables for word accesses. If both bits are low, a read is performed. If
ext_we[1] is high, the contents of ext_d[15:8] are written, and if
ext_we[0] is high, the contents of ext_d[7:0] are written. If both bits are
high, both data bytes are written.
0 Start Access to Extended Memory. Write a ‘1’ to this bit to start the
access to the extended memory registers. This bit is automatically
cleared when the access is complete.
Table 45. Extended Memory Data High (Big Endian) (EMDH_BE) (36h)
Name
ext_d[15:8]
Bit Pos.
7:0
Type
RW
Reset
Description
0 Extended Access Data High. The most significant byte of data to be
written to extended memory is written here before the extended write
begins. The most significant byte of data read from extended memory is
available here after the extended read is complete.
Table 46. Extended Memory Data Low (Big Endian) (EMDL_BE) (37h)
Name
ext_d[7:0]
Bit
Pos.
7:0
Type Reset
Description
RW 0 Extended Access Data Low. The least significant byte of data to be
written to extended memory is written here before the extended write
begins. The least significant byte of data read from extended memory is
available here after the extended read is complete.
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