T8207 Datasheet, PDF (75/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
13 JTAG Test Access Port
A 5-pin test access port, consisting of the jtag_tclk, jtag_tms, jtag_tdi, jtag_tdo, and jtag_trst signals, provides the
standard interface to the test logic. The jtag_trst signal is active-low and resets the JTAG circuitry. When jtag_trst is
high, the JTAG interface is enabled. If the JTAG port is not used, jtag_trst should be tied low.
JTAG may be used only to test the inputs, outputs, and their connection to the printed-wiring board. In JTAG, serial
bit patterns are shifted into the device through the jtag_tdi pin, and the results can be observed at the I/O and at
the corresponding JTAG serial output, jtag_tdo. Since this JTAG conforms to the JTAG standard, the jtag_tdi and
jtag_tdo may be linked to the JTAG port of other devices for systemic testing. The boundary-scan description lan-
guage may be found on the Agere website.
13.1 Instruction Register
The instruction register (IR) is 3 bits in length. The instructions are defined in Table 21.
Table 21. Instruction Register
Instruction
EXTEST
SAMPLE
Reserved
BYPASS
Binary Code
Description
“000”
“001”
“010”—“110”
“111”
Places the boundary-scan register in extest mode.
Places the boundary-scan register in sample mode.
Reserved.
Places the bypass register in the scan chain.
Agere Systems Inc.
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