T8207 Datasheet, PDF (147/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
19 Timing Requirements (continued)
Table 135. Nonmultiplexed Intel Mode Write Access Timing
Symbol
Parameter
Min
t1 write_access_active Falling Edge to a[7:0] and d[7:0] Valid
—
t2 rdy_dtack* Rising Edge to write_access_active Rising Edge
0
t3 rdy_dtack* Rising Edge to a[7:0] and d[7:0] Invalid
0
t4 write_access_active Falling Edge to rdy_dtack* Falling Edge
0
t5 rdy_dtack* Low Pulse Width¹
—
t6 write_access_active Rising Edge to rdy_dtack* 3_state
0
t7 write_access_active Rising Edge to write_access_active Fall- 25
ing Edge
1. See access times in Table 10.
Note: The term pclkp in the table represents the period of pclk in ns.
Typ
Max
Unit
— 2 x pclkp – 4 ns
—
—
ns
—
—
ns
—
12
ns
—
—
—
—
5
ns
—
—
ns
Table 136. Nonmultiplexed Intel Mode Read Access Timing
Symbol
Parameter
t1 read_access_active Falling Edge to a[7:0]
t2 rdy_dtack* Rising Edge to read_access_active Rising
Edge
t3 rdy_dtack* Rising Edge to a[7:0] Invalid
t4 read_access_active Falling Edge to rdy_dtack* Falling
Edge
t5 rdy_dtack* Low Pulse Width¹
t6 read_access_active Rising Edge to d[7:0] Invalid
t7 d[7:0] Valid to rdy_dtack* Rising Edge
t8 read_access_active Falling Edge to d[7:0] Drive
t9 read_access_active Rising Edge to read_access_active
Falling Edge
1. See access times in Table 10.
Note: The term pclkp in the table represents the period of pclk in ns.
Min
Typ
Max
Unit
—
— 2 x pclkp – 4 ns
0
—
—
ns
0
—
—
ns
0
—
12
ns
—
—
0
—
pclkp – 4 —
3 x pclkp – 4 —
25
—
—
—
5
ns
—
ns
—
ns
—
ns
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