T8207 Datasheet, PDF (62/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
10 Cell Bus Interface (continued)
10.5 Cell Bus Monitoring
Every T8207 device monitors the cell bus for proper operation. The monitoring section of the T8207 checks for the
presence of the read clock, the write clock, and the frame synchronization signal. The cb_wc_miss bit in the main
interrupt status 1 register (address 0102h) is set when the write clock is inactive for 32 mclk cycles. Likewise, the
cb_rc_miss bit in the main interrupt status 1 register is set when the read clock is inactive for 32 mclk cycles. In
addition, the cb_fs_miss bit in the main interrupt status 1 register is set when the frame synchronization signal is
inactive for greater than 16 cell bus read clock cycles for 16-user mode or for greater than 32 read clock cycles for
32-user mode. This bit is also set when the cell bus write clock is inactive for 32 mclk cycles.
When cells arrive from the cell bus, the cell bus monitoring section of the receiving device calculates the bit inter-
leave parity value over the 54-byte field from the first tandem routing header byte through the final payload byte. If
this calculated value does not match the value in bits 24 through 31 of the final clock cycle of the frame, the cell is
discarded.
The T8207 detects when a device asserts transmission requests and is not granted permission within a program-
mable time period. The cb_grnt_to bit in the main interrupt status 1 register (address 0102h) is set when a device
has not been granted permission to transmit within the number of frames programmed in the cb_req_to bits of the
main configuration 3 register (address 0116h).
10.6 GTL+ Logic
For the T8207, the cell bus data, frame sync, and acknowledge signals use onboard GTL+ transceivers, and the
cell bus clock signals use onboard GTL+ receivers. The GTL+ bus drivers are open drain and require terminating
resistors at both ends of each line. The terminating resistor (R) may be from 40 Ω to 50 Ω and should be pulled up
to 1.5 V ± 10% (VTT). The actual value of the terminating resistors should be chosen to match the bus line imped-
ance. Figure 17A below illustrates the terminating resistors and the configuration of one GTL+ bus line. The termi-
nation resistors are typically placed at the ends of the bus of the backplane.
The signal rise and fall times from the transceivers are carefully controlled to minimize out of band signals without
affecting the overall transmission rates. These controlled signal edges, in addition to proper resistive line termina-
tion, minimize noise and ringing. The slew rate of the GTL+ buffers can be programmed using bits [2:0] of register
2Eh.
The GTL+ receiver compares its input signal to a voltage reference, cb_vref, to determine the logic level of the
input. The value of the voltage reference is 2/3 VTT and is created using the voltage divider shown in Figure 17B.
The 1 kΩ resistors are 1% because the cb_vref voltage must track VTT by 1%. The 0.01 µF capacitor is a decou-
pling capacitor on the cb_vref input.
VTT
VTT
VTT
1 kΩ ± 1%
R
R
cb_vref
1 kΩ ± 1%
0.01 µF
CelXpres
T8207
CelXpres
T8207
CelXpres
T8207
5-8011a (F)
A. GTL+ Bus with Terminating Resistors
cb_vref_vss
1 kΩ ± 1%
5-8012a(F)
B. GTL+ Threshold Voltage Reference
Figure 17. GTL+ External Circuitry
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