T8207 Datasheet, PDF (77/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
13 JTAG Test Access Port (continued)
Table 22. Boundary-Scan Register Descriptions (continued)
Boundary-Scan
Register Bit
Name
Pin Name
Description
84
85
86
87
88
89
90—101
102—103
RDY_DTACK_N_OE
RDYDTACK
SEL_N
WR_N
DEVHIZ_N_HIGH_DRIVE
INT_IRQ
SD_A(0:11)
SD_BS(0:1)
—
rdy_dtack*
sel*
wr*_ds*
—
int_irq*
sd_a[0:11]
sd_bs[0:1]
RDYDTACK is high impedance when
RDY_DTACK_N_OE = 0.
3-statable output.
Input.
Input.
INT_IRQ, SD_A(11:0), SD_BS(1:0), SD_CAS_N,
SD_RAS_N, and SD_WE_N are high impedance
when DEVHIZ_N_HIGH_DRIVE = 0.
3-statable output.
3-statable output.
3-statable output.
104
105
106
107
108—123
124
125
126
127
128
129—146
147—148
149
150—157
158
SD_CAS_N
SD_CLK_OE
SD_CLK
SD_D_OE
SD_D(0:15)
SD_RAS_N
SD_WE_N
TR_CONT_OE
TR_OE_N
TR_WE_N
TR_A(0:17)
TR_CS(0:1)
TR_D_OE
TR_D(0:7)
U_RXADDR_OE
sd_cas*
—
sd_clk
—
sd_d[0:15]
sd_ras*
sd_we*
—
tr_oe*
tr_we*
tr_a[0:17]
tr_cs*[0:1]
—
tr_d[0:7]
—
3-statable output.
SD_CLK is an input when SD_CLK_OE = 0.
Bidirectional.
SD_D(15:0) are inputs when SD_D_OE = 0.
Bidirectional.
3-statable output.
3-statable output.
TR_OE_N, TR_WE_N, TR_A(17:0), and
TR_CS(1:0) are high impedance when
TR_CONT_OE = 0.
3-statable output.
3-statable output.
3-statable output.
3-statable output.
TR_D(7:0) are inputs when TR_D_OE = 0.
Bidirectional.
U_RXADD(4:0) are inputs when U_RXADDR_OE
= 0.
159—163
164
165
166—168
169
170
171—178
U_RXADD(0:4)
U_RXCLAV0_OE
U_RXCLV0
U_RXCLV1—U_RXCLV3
U_RXCLK_OE
U_RXCLK
U_RXDAT(0:7)
u_rxaddr[0:4] Bidirectional.
—
U_RXCLV0 is an input when U_RXCLAV0_OE =
0.
u_rxclav[0] Bidirectional.
u_rxclav[1:3] Input.
—
U_RXCLK is an input when U_RXCLK_OE = 0.
T1
Bidirectional.
u_rxdata[0:7] Input.
179
U_RXENB0_OE
—
U_RXENB(0) is an input when U_RXENB0_OE =
0.
Agere Systems Inc.
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