T8207 Datasheet, PDF (133/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
14 Registers (continued)
Table 118. Queue X (QX) (0440h to 04BEh)
Name
queueX_rd_en
Bit Pos. Type
0
RW
queueX_wr_en
1
RW
queueX_fecn_en
2
RW
queueX_clp_en
3
RW
Reserved
7:4
RO
queueX_fecn_lim
8
ROL
queueX_clp_lim
9
ROL
queueX_ovrn
10
ROL
queueX_emp
11
queueX_fecn_lim_ie 12
ROL
RW
queueX_clp_lim_ie 13
RW
queueX_ovrn_ie
14
RW
Reset
0
Description
Queue X Read Enable. If this bit is ‘1,’ the queue is enabled
for read operations. When any configuration bits are
changed, this bit must be ‘0.’
Note: To prevent corruption of data, this bit must be cleared
in unused queues.
0 Queue X Write Enable. If this bit is ‘1,’ the queue is enabled
for write operations. When any configuration bits are
changed, this bit must be ‘0.’
Note: To prevent corruption of data, this bit must be cleared
in unused queues.
0 Queue X FECN Enable. If this bit is ‘1,’ the forward explicit
congestion notification (FECN) feature is enabled.
0 Queue X CLP Enable. If this bit is ‘1,’ the cell loss priority
(CLP) feature is enabled.
0 Reserved.
0 Queue X FECN Limit Reached. This bit is set when the
FECN limit has been reached in the queue. An interrupt is
generated if the corresponding enable bit is set.
0 Queue X CLP Limit Reached. This bit is set when the CLP
limit has been reached in the queue. An interrupt is gener-
ated if the corresponding enable bit is set.
0 Queue X Overrun. This bit is set when the queue overruns.
An interrupt is generated if the corresponding enable bit is
set.
0 Queue X Empty. This bit is set when the queue is empty. An
interrupt is generated if the corresponding enable bit is set.
0 Queue X FECN Limit Reached Interrupt Enable. An inter-
rupt is generated if this bit and the corresponding status bit
are set. The interrupt is generated until this bit or the corre-
sponding status bit is reset.
0 Queue X CLP Limit Reached Interrupt Enable. An inter-
rupt is generated if this bit and the corresponding status bit
are set. The interrupt is generated until this bit or the corre-
sponding status bit is reset.
0 Queue X Overrun Interrupt Enable. An interrupt is gener-
ated if this bit and the corresponding status bit are set. The
interrupt is generated until this bit or the corresponding sta-
tus bit is reset.
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