T8207 Datasheet, PDF (22/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
5 PLL Configuration
The frequency of the device’s main clock (mclk) is derived from the clock at the xtalin input (pclk) and is given by
the following equation when the PLL is engaged:
fmclk = fpclk x ₍---₂-----_×-----₍--_M-----_O----⁽-_D--^M---₈---⁺-₍--_N--²----⁾₊-----₁----₎---₊-----₁----₎--₎-
Note: When the PLL is engaged, mclk is the output of the PLL.
M and N are the pll_m[4:0] and pll_n[2:0] counter values in the mclk PLL configuration 1 register (address 2Bh) and
must be set so that the voltage-controlled oscillator (VCO) operates in the appropriate range. The maximum value
for fmclk is 100 MHz. The valid range for M is between 2 and 22 inclusive, and the valid range for N is between 0
and 7 inclusive. When multiple sets of values can achieve the desired result, choose the lowest value of M and the
corresponding value for N.
Note: The output of the PLL must always be at least 50 MHz.
The loop filter must be set properly for correct operation of the PLL. The proper setting of the loop filter bits, lf[3:0],
in the mclk PLL configuration 0 register (address 2Ah) is determined by the chosen value for M. The following table
lists the lf[3:0] settings for given values of M. Typical PLL lock-in time is 50 µs.
Table 9. Loop Filter Register Settings
M
22
16—21
10—15
6—9
4—5
2—3
Mclk PLL Configuration 0
(2Ah) lf[3:0]
“0111”
“0110”
“0101”
“0100”
“0011”
“0010”
PLL Configuration Example:
Given a pclk frequency of 50 MHz and a desired mclk frequency of 100 MHz, the proper values of M, N, and lf[3:0]
are the following:
M=2
N=7
lf[3:0] = “0010”
The bypass PLL (bypb) and PLL enable (pllen) bits are used to select the source of mclk for the T8207. To select
the output of the PLL as the clock, both bits must be programmed to ‘1,’ and to select pclk as the clock, both bits
must be programmed to ‘0.’
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