T8207 Datasheet, PDF (56/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
10 Cell Bus Interface (continued)
10.2 Cell Bus Frames
A cell bus frame is always 16 clock cycles. The cell bus frame has three sections (request, bus cell, and grant).
During the request section, which is the first clock cycle of the frame, 16 devices assert their transmission requests
onto the bus. During the bus cell section, which is the next 14 clock cycles, a cell is transmitted on the cell bus. This
bus cell includes the cell bus routing header, the optional tandem routing header, and the 52-byte body of the cell.
During the grant section, which is the last clock cycle of the frame, the grant is asserted, indicating which device
may transmit its cell during the next frame. Also, during this last clock cycle, a parity vector is placed on the bus by
the transmitting device so that error detection can be performed on the cell. Figure 14 illustrates the format for the
cell bus frame.
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16 15
0
CYCLE 0 U15 U14 U13 U12 U11 U10 U9 U8 U7 U6 U5 U4 U3 U2 U1 U0
CYCLE 1
CELL BUS ROUTING HEADER
TANDEM ROUTING HEADER
CYCLE 2
GFC/
VPI[11:8]
VPI[7:0]
VCI[15:0]
C
PTI L
P
CYCLE 3
PAYLOAD BYTE 0
PAYLOAD BYTE 1
PAYLOAD BYTE 2
PAYLOAD BYTE 3
CYCLE 4
PAYLOAD BYTE 4
PAYLOAD BYTE 5
PAYLOAD BYTE 6
PAYLOAD BYTE 7
CYCLE 5
PAYLOAD BYTE 8
PAYLOAD BYTE 9
PAYLOAD BYTE 10
PAYLOAD BYTE 11
CYCLE 6
PAYLOAD BYTE 12
PAYLOAD BYTE 13
PAYLOAD BYTE 14
PAYLOAD BYTE 15
CYCLE 7
PAYLOAD BYTE 16
PAYLOAD BYTE 17
PAYLOAD BYTE 18
PAYLOAD BYTE 19
CYCLE 8
PAYLOAD BYTE 20
PAYLOAD BYTE 21
PAYLOAD BYTE 22
PAYLOAD BYTE 23
CYCLE 9
PAYLOAD BYTE 24
PAYLOAD BYTE 25
PAYLOAD BYTE 26
PAYLOAD BYTE 27
CYCLE 10
PAYLOAD BYTE 28
PAYLOAD BYTE 29
PAYLOAD BYTE 30
PAYLOAD BYTE 31
CYCLE 11
PAYLOAD BYTE 32
PAYLOAD BYTE 33
PAYLOAD BYTE 34
PAYLOAD BYTE 35
CYCLE 12
PAYLOAD BYTE 36
PAYLOAD BYTE 37
PAYLOAD BYTE 38
PAYLOAD BYTE 39
CYCLE 13
PAYLOAD BYTE 40
PAYLOAD BYTE 41
PAYLOAD BYTE 42
PAYLOAD BYTE 43
CYCLE 14
PAYLOAD BYTE 44
PAYLOAD BYTE 45
PAYLOAD BYTE 46
PAYLOAD BYTE 47
CYCLE 15
BIT INTERLEAVE PARITY
—————————————————
G
P
G
E
GRANT NUMBER
Figure 14. Cell Bus Frame Format (Bit Positions for 16 User Mode)
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