T8207 Datasheet, PDF (129/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
14 Registers (continued)
Table 107. SDRAM Configuration (SCF) (0408h)
Name
col_num
cas_lat
ras2cas
cas2pre
pre2cmd
ref2cmd
Reserved
Bit Pos.
1:0
2
4:3
6:5
8:7
10:9
15:11
Type Reset
Description
RW 0 Column Number. These bits are used to indicate the number of col-
umns in the SDRAM.
“100” = 256 columns
“01” = 512 columns
“10” = 1024 columns
“11” = reserved
RW 0 CAS Latency. This bit is used to indicate the CAS latency of the
SDRAM based on the clock frequency and speed grade of the device.
‘0’ = 2 cycles
‘1’ = 3 cycles
RW 2h RAS Inactive to CAS Active Delay. These bits specify the minimum
time in SDRAM clock cycles from RAS going inactive to CAS going
active.
“01” = reserved
“10” = 2 clock cycles
“11” = 3 clock cycles
“00” = 4 clock cycles
RW 1 CAS Inactive to Precharge Active Delay. These bits specify the min-
imum time in SDRAM clock cycles from CAS going inactive to the pre-
charge command going active.
“01” = 1 clock cycles
“10” = 2 clock cycles
“11” = 3 clock cycles
“00” = 4 clock cycles
RW 2h Precharge Inactive to Next Command Active Delay. These bits
specify the minimum time in SDRAM clock cycles from the precharge
command going inactive to next command going active.
“01” = 1 clock cycles
“10” = 2 clock cycles
“11” = 3 clock cycles
“00” = 4 clock cycles
RW 0 CBR Refresh Inactive to Next CBR Refresh Command Active
Delay. These bits specify the minimum time in SDRAM clock cycles
from the refresh command going inactive to next refresh command
going active. The minimum time from the refresh command to any
other command is 15 clock cycles.
“00” = 15 clock cycles
“01” = reserved
“10” = 3 clock cycles
“11” = 7 clock cycles
RO
0 Reserved.
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