T8207 Datasheet, PDF (145/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
19 Timing Requirements
The following section describes the timing requirements. Capacitve loading is in the range of 10 pF to 50 pF,
unless otherwise specified.
Some timing requirements are dependent on the frequency of pclk or mclk. The terms mclkp and pclkp refer to the
period of their respective clocks in ns when used in the following tables.
Table 133. Input Clocks
Clock Name Frequency
(Max)
cb_wc*
cb_rc*
u_rxclk
u_txclk
66 MHz
66 MHz
50 MHz
50 MHz
Voltage Level
High
—
—
2.0 V
2.0 V
Low
—
—
0.8 V
0.8 V
Rise Time
(Max)
—
—
4.0 ns
4.0 ns
Fall Time
(Max)
—
—
4.0 ns
4.0 ns
Pulse Width (Min)
High
6.06 ns
6.06 ns
8 ns
8 ns
Low
6.06 ns
6.06 ns
8 ns
8 ns
Note: The cell bus write clock (cb_wc*) should be delayed 1.5 ns to 4 ns relative to the cell bus read clock (cb_rc*) to ensure sufficient data hold
time.
Table 134. Output Clocks
Clock Name Frequency (Max)
Rise Time (Max) Fall Time (Max)
sd_clk
u_rxclk
u_txclk
100 MHz
50 MHz
50 MHz
1.0 ns
2.0 ns
2.0 ns
1.0 ns
2.0 ns
2.0 ns
Pulse Width (Min)
High
Low
4 ns
4 ns
8 ns
8 ns
8 ns
8 ns
Load
15 pF
40 pF
40 pF
Agere Systems Inc.
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