T8207 Datasheet, PDF (105/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
14 Registers (continued)
Table 70. Misrouted LUT 1 (MLUT1) (0142h)
Name
mis_cell_lut_sel
Bit Pos.
15:0
Type
RW
Reset
Description
FFFFh Misrouted Cell LUT Select. Each bit in this field repre-
sents one of 16 look-up table memory spaces. The least
significant bit is LUT memory space 0. If the correspond-
ing bit is ‘1,’ misrouted cells from the LUT memory space
are monitored.
Table 71. Misrouted LUT 2 (MLUT2) (0144h)
Name
mis_cell_clr
mis_cell_latch
Reserved
lst_mis_cell_lut
Reserved
Bit Pos. Type
0
WO
1
RO
3:2
RO
7:4
RO
15:8 RO
Reset
Description
0 Misrouted Cell Header Clear. Write ‘1’ to this bit to clear
the previously latched misrouted cell header. The ‘1’ will
pulse for one clock cycle and will clear to ‘0’ automatically.
0 Misrouted Cell Header Latched. If this bit is set to ‘1,’ a
misrouted cell was detected and is stored to the
mis_cell_header bits.
0 Reserved.
0 Last Misrouted Cell LUT. These bits indicate the LUT
memory space from which the last misrouted cell was
detected.
0 Reserved.
Table 72. Misrouted Cell Header High (MCHH) (0146h)
Name
Bit Pos. Type
mis_cell_header[31:16] 15:0 RO
Reset
Description
0 Misrouted Cell Header Bits [31:16]. These bits are cell
header bits [31:16] from the first misrouted cell received
after the mis_cell_clr bit was set. A cell is considered mis-
routed if its A and I bits are “00,” if its VCI is out of range,
or if the lutX_vpi_chk bit is ‘1’ and the unused VPI bits in
the incoming cell header are not all zero.
Table 73. Misrouted Cell Header Low (MCHL) (0148h)
Name
mis_cell_header[15:0]
Bit Pos. Type
15:0 RO
Reset
Description
0 Misrouted Cell Header Bits [15:0]. These bits are cell
header bits [15:0] from the first misrouted cell received
after the mis_cell_clr bit was set. A cell is considered mis-
routed if its A and I bits are “00,” if its VCI is out of range,
or if the lutX_vpi_chk bit is ‘1’ and the unused VPI bits in
the incoming cell header are not all zero.
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