T8207 Datasheet, PDF (64/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
11 SDRAM Interface
For outgoing UTOPIA cells, the TX UTOPIA cell buffer supports 64 queues. These queues are separated into
16 queue groups, each consisting of four different priority queues as described in Section 9.2.2, Outgoing ATM
Mode (Cells Sent by T8207). This cell buffer holds 128 outgoing cells. Additional buffering is provided by an exter-
nal SDRAM. Connection to an external SDRAM is selected by clearing the sdram_bypass bit in the main configura-
tion 1 register (address 0100h).
If the SDRAM is not used, it is bypassed by setting the sdram_bypass bit in the main configuration 1 register at
start-up. When bypassed, only queue 0 of the 64 queues in the TX UTOPIA cell buffer is used. The only buffering
available in this mode is the 128-cell internal memory (TX PHY FIFO) and up to 128 cells from queue 0 of the TX
UTOPIA cell buffer. The TX PHY FIFO overflows only if the TX UTOPIA cell buffer is full, and as a result, the TX
PHY FIFO is also full. The setting of the div_queue bits in the main configuration 2 register (address 0112h) deter-
mines the number of cell locations allocated to queue 0 of the TX UTOPIA cell buffer. Be sure to program these bits
to “101” to maximize buffering.
11.1 Memory Configuration
The SDRAM interface supports from 2 Mbytes to 32 Mbytes of memory. This memory size is realized using 16 Mbit
or 64 Mbit devices. Table 17 below outlines the various memory configurations supported.
Table 17. Supported Memory Configurations
Number of
Devices
1
2
4
1
2
4
Device Memory Size and Data
Bus Organization
16 Mbit, 16-bit data bus
16 Mbit, 8-bit data bus
16 Mbit, 4-bit data bus
64 Mbit, 16-bit data bus
64 Mbit, 8-bit data bus
64 Mbit, 4-bit data bus
Number of
Columns
256
512
1024
256
512
1024
Number of
Banks
2
2
2
4
4
4
Number of
Rows
2048
2048
2048
4096
4096
4096
Total
Memory
2 Mbyte
4 Mbyte
8 Mbyte
8 Mbyte
16 Mbyte
32 Mbyte
11.2 Powerup Sequence
The powerup sequence for the SDRAM must be performed manually before the SDRAM is enabled. Using the idle
state 1 and 2 registers (addresses 0420h and 0422h), the manual access state 1 and 2 registers (addresses 0424h
and 0426h), and the gen_man_acc bit in the SDRAM control register (address 0400h), follow the powerup com-
mand sequence prescribed by the SDRAM manufacturer. The T8207 does not control the chip select, the clock
enable, and the DQM inputs to the SDRAM. These signals should be externally tied to the appropriate logic level or
external control signal.
To manually execute SDRAM commands, first set up the idle values for CAS*, RAS*, WE*, bank select (BS), and
the address signals using the cas_idle, ras_idle, we_idle, bs_idle[1:0], and addr_idle[11:0] bits in the idle state 1
and 2 registers. Then manually set up the value of these signals for the first SDRAM command using the cas_man,
ras_man, we_man, bs_man[1:0], and addr_man[11:0] bits in the manual access state 1 and 2 registers. Finally,
write a ‘1’ to the gen_man_acc bit in the SDRAM control register. Writing this ‘1’ drives the CAS, RAS, WE*, BS,
and address values (in the manual access state 1 and 2 registers) onto the associated pins, for one SDRAM clock
cycle. After the one clock cycle, these signals return to their idle state. Repeat this process, making sure minimum
timing between commands is met, until the powerup process has been completed.
In the powerup sequence, configure the mode register of the SDRAM for a burst length of one and a CAS latency
of two or three. With a burst length of one, sequential and interleave addressing behave the same, so the SDRAM
may be configured for either addressing mode.
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