T8207 Datasheet, PDF (124/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
14 Registers (continued)
Table 99. PPD Information 7 (PPDI7) (0212h)
Name
Bit Pos.
ppd_pnt0_sel[5:0] 5:0
ppd_pnt1_sel[5:0] 11:6
Reserved
15:12
Type
RW
RW
RO
Reset
Description
X PPD Pointer 0 Select.
The ppd_pnt0_sel[5:0] bit field selects which bit of the cell
header, the cell bus routing header, or the tandem routing header
is used as this offset bit.
X PPD Pointer 1 Select.
The ppd_pnt1_sel[5:0] bit field selects which bit of the cell
header, the cell bus routing header, or the tandem routing header
is used as this offset bit.
PPD Pointer 0 and 1 Select.
The PPD pointer select bits are used to create an offset into the
PPD state memory. The PPD state memory is used to keep track
of AAL5 virtual channels for partial packet discard. Up to 8192 vir-
tual channels may be supported with these select fields. The
ppd_pnt12_sel[5:0] bits select the most significant bit of the PPD
state memory offset, and the ppd_pnt0_sel[5:0] bits select the
least significant bit of the offset. A value of zero to 31 selects bits
in the cell header where zero is the CLP bit and 31 is the most
significant bit of the GFC/VPI field. A value of 32 to 47 selects bits
in the tandem routing header where 32 is the least significant bit
and 47 is the most significant bit. A value of 48 to 63 selects bits
in the cell bus routing header where 48 is the least significant bit
and 63 is the most significant bit. The value, “110000,” is a spe-
cial case and may be used to force the value of this bit to ‘0.’ If
this bit is forced to zero, the bit position in the resultant pointer is
always ‘0’ and is not extracted from the received cell.
0 Reserved.
Table 100. PPD Memory Write (PPDMW) (0418h)
Name
write_pul
write_val
write_addr
Reserved
Bit Pos.
0
1
14:2
15
Type
RW
RW
RW
RO
Reset
Description
0 Write Pulse. If a ’1’ is written to this bit, a single bit will be written
to the PPD memory. The value of the bit is obtained from the
write_val bit, and the address in the PPD memory is obtained
from the write_addr bits. The write_pul bit is cleared by hardware
when the write is complete.
0 Write Value. This bit contains the value to be written to the PPD
state memory bit.
0 Write Address. These bits contain the address of the bit in PPD
memory. This address will be used when a write is performed.
This address corresponds to the offset from the cell header, cell
bus header, and tandem routing header as determined from the
PPD point select bits. An address of all zeros will point to the
most significant bit of word 0, and an address of all ones will point
to the least significant bit of word1FF.
0 Reserved.
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