T8207 Datasheet, PDF (107/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
14 Registers (continued)
Table 79. LUT X Configuration/Status (LUTXCFS) (0320h to 033Eh)
Name
Bit Pos. Type Reset
Description
lut_en
0
RW
0 LUT Memory Space Enable. If this bit is ‘1,’ the LUT memory
space is enabled. When this bit is ‘0,’ cells from the associated
PHY port are discarded, are not flagged as misrouted, and are
not counted as a received cell.
Note: When 16 or less PHY ports are used, each PHY port has
its own look-up table memory space. For 16 or less PHY
ports, PHY port 0 uses LUT 0 memory space, PHY port
1 uses LUT 1 memory space, and so on. When greater
than 16 PHY ports are used, even and odd PHY ports
must share the look-up memory space. For greater than
16 PHY ports, PHY ports 0 and 1 use LUT 0 memory
space, PHY ports 2 and 3 use LUT 1 memory space,
PHY ports 4 and 5 use LUT 2 memory space, and so on.
Reserved
mis_cell
3:1
RO
0 Reserved.
4
ROL
0 Misrouted Cell to LUT. This bit is set when a cell’s translation
record has its A and I bits equal to ‘0.’ An interrupt is generated
if the corresponding enable bit is set.
vci_or
vpi_or
5
ROL
0 VCI Out of Range. This bit is set when an incoming cell’s VCI
is greater than the allowed range. An interrupt is generated if
the corresponding enable bit is set.
6
ROL
0 VPI Out of Range. This bit is set when one of the incoming
cell’s unmasked VPI bits is not ‘0’ and the lutX_vpi_chk bit
equals ‘1.’ An interrupt is generated if the corresponding
enable bit is set.
Reserved
mis_cell_ie
9:7
RO
0 Reserved.
10
RW
0 Misrouted Cell to LUT Interrupt Enable. An interrupt is gen-
erated if this bit and the corresponding status bit are set. The
interrupt is generated until this bit or the corresponding status
bit is reset.
vci_or_ie
11
RW
0 VCI Out of Range Interrupt Enable. An interrupt is generated
if this bit and the corresponding status bit are set. The interrupt
is generated until this bit or the corresponding status bit is
reset.
vpi_or_ie
12
RW
0 VPI Out of Range Interrupt Enable. An interrupt is generated
if this bit and the corresponding status bit are set. The interrupt
is generated until this bit or the corresponding status bit is
reset.
Reserved
15:13
RO
0 Reserved.
The letter X in the register name represents the 16 PHY port look-up tables. The addresses of the 16 configuration/
status registers are shown below.
Register Name
LUT 0 Configuration/Status
LUT 1 Configuration/Status
Register
Address
0320h
0322h
Register Name
LUT 8 Configuration/Status
LUT 9 Configuration/Status
Register
Address
0330h
0332h
LUT 2 Configuration/Status
LUT 3 Configuration/Status
LUT 4 Configuration/Status
LUT 5 Configuration/Status
LUT 6 Configuration/Status
LUT 7 Configuration/Status
0324h
0326h
0328h
032Ah
032Ch
032Eh
LUT 10 Configuration/Status
LUT 11 Configuration/Status
LUT 12 Configuration/Status
LUT 13 Configuration/Status
LUT 14 Configuration/Status
LUT 15 Configuration/Status
0334h
0336h
0338h
033Ah
033Ch
033Eh
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