T8207 Datasheet, PDF (73/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
11 SDRAM Interface (continued)
11.6 SDRAM Throughput
The SDRAM clock frequency must be fast enough for cell transfers, to and from the SDRAM, to occur without over-
runs to the TX PHY FIFO or underruns to the TX UTOPIA cell buffer. Using the default values for ras2cas, cas2pre,
and pre2cmd, thirty-five clock cycles are required to transfer one cell (56 bytes) into or out of the SDRAM. The
assumed efficiency rate is 90%. Therefore, the number of cells per second that can be read or written into the
SDRAM is calculated using the following equation:
Cell Rate = (fmclk/35 cycles per cell x 90%)
where fmclk is the frequency of the SDRAM clock.
The maximum UTOPIA and cell bus bandwidths must be calculated to ensure that the SDRAM clock frequency
supports these bandwidths. For example, assume that the total bandwidth on the UTOPIA bus is 64 Mbits/s and
that the cell bus clock rate is 33 MHz. The maximum number of cells per second that the cell bus can send is:
-------------3---3-----M------H----z-------------- = 2.06 Mcells per second.
16 cycles per cell
On the UTOPIA port, the total number of cells that can be sent is:
5----3-----b---y---t--e---s-----p---e---6r---4-c---e-M--l--l-b--×^{-i--t-s8---/--sb----i-t--s----p----e---r----b---y---t--e-- = 151 Kcells per second.}
Thus, the total number of cells per second from the cell bus and to the UTOPIA bus is 2.21 Mcells per second. For
the cell rate equation above, the required SDRAM clock frequency is:
2----.-2----1-----M-----c---e---l-l--s----p----e---r----s---e---c---o----n---d-- _{* 35 cycles per cell = 86 MHz.}
0.9
This is a worst-case example and assumes that all potential cells on the cell bus are going to this one device. The
SDRAM frequency calculation produces a lower frequency if the actual system characteristics are considered and
if the distribution of cells is controlled.
Agere Systems Inc.
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