T8207 Datasheet, PDF (106/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
14 Registers (continued)
14.3.2 UTOPIA Registers
Table 74. HEC Interrupt Status 1 (HIS1) (0302h)
Name
hec_err[31:16]
Bit Pos. Type
15:0
RW
Reset
0
Description
HEC Error. Each bit in this field represents one of the upper
16 PHY ports where the most significant bit is port 31 and the
least significant bit is port 16. The associated bit is set when an
HEC error is detected on the PHY port. An interrupt is gener-
ated if the corresponding enable bit is set. When a HEC error
occurs, the cell is still counted as received and is translated
and routed.
Table 75. HEC Interrupt Enable 1 (HIE1) (0304h)
Name
Bit Pos. Type
hec_err_ie[31:16] 15:0
RW
Reset
0
Description
HEC Error Interrupt Enable. An interrupt is generated if this
bit and the corresponding status bit are set. The interrupt is
generated until this bit or the corresponding status bit is reset.
Table 76. HEC Interrupt Status (HIS) (0306h)
Name
hec_err[15:0]
Bit Pos. Type
15:0 ROL
Reset
0
Description
HEC Error. Each bit in this field represents one of the lower
16 PHY ports where the most significant bit is port 15 and the
least significant bit is port 0. The associated bit is set when an
HEC error is detected on the PHY port. An interrupt is gener-
ated if the corresponding enable bit is set. When a HEC error
occurs, the cell is still counted as received and is translated
and routed.
Table 77. HEC Interrupt Enable (HIE) (0308h)
Name
Bit Pos. Type
hec_err_ie[15:0] 15:0
RW
Reset
0
Description
HEC Error Interrupt Enable. An interrupt is generated if this
bit and the corresponding status bit are set. The interrupt is
generated until this bit or the corresponding status bit is reset.
Table 78. LUT Interrupt Service Request (LUTISR) (030Eh)
Name
Bit Pos. Type
lut_int_serv[15:0] 15:0
RO
Reset
0
Description
LUT Interrupt Service. Each bit in this field represents one of
16 LUT configuration/status registers. The least significant bit
represents LUT 0 configuration/status register. If the corre-
sponding bit is ‘1,’ the specific LUT configuration/status register
has interrupt status bits that need servicing.
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