T8207 Datasheet, PDF (48/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
9 UTOPIA Interface (continued)
9.5 Shared UTOPIA Mode
The shared UTOPIA mode supports up to 16 PHY ports using only 32 queues, and it allows two T8207 devices on
different cell buses to share the same UTOPIA bus. This shared mode can be used to provide redundancy or to
increase the cell bus system capacity. One T8207 device is configured as master and the other as slave, using the
slave_en bit in the main configuration/control register (address 0110h). The master and the slave communicate to
each other through the shared UTOPIA output (u_shr_o) and input (u_shr_i) pins. For the master, u_shr_o func-
tions as the grant output, and u_shr_i, as the request input. For the slave, u_shr_o functions as the request output,
and u_shr_i, as the grant input. Only T8207 devices configured for ATM mode may be used in shared UTOPIA
mode. This configuration is supported for both UTOPIA level 1 and 2 configurations. The configuration for the
addr_clav_en bits must be the same in both devices in MCF2 (0112h) and port_rte (0178h to 017Eh) registers.
Note: The T8207 will support shared UTOPIA mode for only up to 32 queues. To use shared UTOPIA with 16 PHY
ports, only 32 queues, shared between even and odd ports can be used, which translates to a zero value for
the T8207_sel bit (Table 59).
The TX UTOPIA cell buffers in the master and the slave may be divided into the same number of queues or differ-
ent number of queues. The mast_queue_in[31:16], mast_queue_in[15:0], slav_queue_in[31:16], and
slav_queue_in[15:0] bits in the master queue 0 (address 015Ch), master queue 1 (address 015Eh), slave queue 0
(address 016Ch), and slave queue 1 (address 016Eh) registers, respectively, must be configured in the master
device. These bits indicate which queues in the master and which queues in the slave are enabled. The master’s
priority algorithm uses this information to determine which waiting cell should be transmitted. The slave queue 0
and 1 registers are ignored in the slave.
The transmit operation in shared UTOPIA mode is illustrated in Figure 13. For the transmit interface, all enable,
start of cell, and data signals occur relative to the low-going start of grant signal from the master. The start of grant
signal occurs every 60 clock cycles and is always preceded by at least six clock cycles of ones.
Both devices transmit on the TX UTOPIA bus; the master arbitrates the bus and grants the slave access via its
u_shr_o pin. When the slave has cells waiting for transmission, it makes a request for each queue (up to 32) that
contains cells. To make this request, the slave pulls its request output low for one clock cycle during the queue’s
request period. The request period for each queue is assigned relative to the master’s start of grant signal. The
request period for queue zero occurs ten clock cycles after the start of grant and is followed by the request period
for queue one. The master uses the received queue number and a priority algorithm to determine if a slave’s cell
should be transmitted before one of its own. Both master and slave have an equal chance to transmit cells if the
cells have equal priority. The master grants the slave’s request by sending 8 bits of serial data, clocked at the rate
of the UTOPIA transmit clock, to its grant output. The first bit is the low-going grant signal. The next 5 bits desig-
nate the queue number of the cell to be transmitted. The queue number is sent most significant bit first. The next bit
is the valid bit; it is low if this grant is valid. Finally, the last bit (R[0]) is reserved for future use. The slave then has
53 cycles or 55 cycles to transmit its cell depending on the mode.
In UTOPIA receive mode, the master controls the UTOPIA bus, and the slave only monitors the bus. Both master
and slave receive all cells and use their individual look-up tables to determine which cells are destined for their cell
bus. The master controls the enable (u_rxenb[3:0]) and address (u_rxaddr[4:0]) signals to the UTOPIA bus. The
slave monitors these signals to determine when the cell starts and which port is sending the cell.
In shared UTOPIA mode, the master always drives the u_rxaddr[4:0], u_txaddr[4:0], u_txsoc, u_rxenb*[3:0], and
u_txenb*[3:0] signals. These signals become high impedance on the slave when the slave_en bit in the main con-
figuration/control register (address 0110h) is set. Both the master and slave drive the u_txprty and u_txdata[7:0]
signals when they transmit a cell; therefore, these signals must transition to a high-impedance state when not
active. Clear the tx_utopia_hi_z bit in the main configuration 1 register (address 0100h) to force the u_txprty and
u_txdata[7:0] signals to a high-impedance state when inactive.
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