T8207 Datasheet, PDF (51/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
9 UTOPIA Interface (continued)
Table 16. Port Numbering for MPHY Configurations
# of
addr
0
1
2
2
3
3
4
4
# of
addr
0
1
2
2
3
3
4
4
# of
clav/enb*
4
4
4
2
2
1
1
2
# of
clav/enb*
4
4
4
2
2
1
1
2
Port 0
enb*[0],
clav[0],
addr = 0
enb*[0],
clav[0],
addr = 0
enb*[0],
clav[0],
addr = 0
enb*[0],
clav[0],
addr = 0
enb*[0],
clav[0],
addr = 0
enb*[0],
clav[0],
addr = 0
enb*[0],
clav[0],
addr = 0
enb*[0],
clav[0],
addr = 0
Port 8
—
enb*[2],
clav[2],
addr = 0
enb*[2],
clav[2],
addr = 0
enb*[1],
clav[1],
addr = 0
enb*[1],
clav[1],
addr = 0
enb*[0],
clav[0],
addr = 8
enb*[0],
clav[0],
addr = 8
enb*[0],
clav[0],
addr = 8
Ports 0—7
Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7
—
—
enb*[0],
clav[0],
addr = 1
—
enb*[0],
clav[0],
addr = 1
—
enb*[0],
clav[0],
addr = 1
enb*[0],
clav[0],
addr = 1
Port 9
—
—
enb*[2],
clav[2],
addr = 1
—
enb*[1],
clav[1],
addr = 1
—
enb*[0],
clav[0],
addr = 9
enb*[0],
clav[0],
addr = 9
enb*[1],
clav[1],
addr = 0
enb*[0],
clav[0],
addr = 2
enb*[0],
clav[0],
addr = 2
enb*[0],
clav[0],
addr = 2
enb*[0],
clav[0],
addr = 2
enb*[0],
clav[0],
addr = 2
enb*[0],
clav[0],
addr = 2
enb*[0],
clav[0],
addr = 2
Port 10
—
enb*[2],
clav[2],
addr = 2
enb*[2],
clav[2],
addr = 2
enb*[1],
clav[1],
addr = 2
enb*[1],
clav[1],
addr = 2
enb*[0],
clav[0],
addr = 10
enb*[0],
clav[0],
addr = 10
enb*[0],
clav[0],
addr = 10
—
enb*[2],
clav[2],
addr = 0
—
enb*[1],
clav[1],
addr = 0
enb*[0],
clav[0],
addr = 3
enb*[1],
clav[1],
addr0
—
enb*[0],
clav[0],
addr = 4
enb*[0], enb*[0],
clav[0], clav[0],
addr = 3 addr = 4
—
enb*[0],
clav[0],
addr = 4
enb*[0], enb*[0],
clav[0], clav[0],
addr = 3 addr = 4
enb*[0], enb*[0],
clav[0], clav[0],
addr = 3 addr = 4
Ports 8—15
Port 11 Port 12
—
—
—
enb*[3],
clav[3],
addr = 0
enb*[2], enb*[3],
clav[2], clav[3],
addr = 3 addr = 0
—
enb*[1],
clav[1],
addr = 4
enb*[1], enb*[1],
clav[1], clav[1],
addr = 3 addr = 4
—
enb*[0],
clav[0],
addr = 12
enb*[0], enb*[0],
clav[0], clav[0],
addr = 11 addr = 12
enb*[0], enb*[0],
clav[0], clav[0],
addr = 11 addr = 12
—
—
enb*[1],
clav[1],
addr = 1
—
enb*[0],
clav[0],
addr = 5
—
enb*[0],
clav[0],
addr = 5
enb*[0],
clav[0],
addr = 5
Port 13
—
—
enb*[3],
clav[3],
addr = 1
—
enb*[1],
clav[1],
addr = 5
—
enb*[0],
clav[0],
addr = 13
enb*[0],
clav[0],
addr = 13
enb*[3],
clav[3],
addr = 0
enb*[1],
clav[1],
addr = 2
enb*[1],
clav[1],
addr = 2
enb*[0],
clav[0],
addr = 6
enb*[0],
clav[0],
addr = 6
enb*[0],
clav[0],
addr = 6
enb*[0],
clav[0],
addr = 6
enb*[0],
clav[0],
addr = 6
Port 14
—
enb*[3],
clav[3],
addr = 2
enb*[3],
clav[3],
addr = 2
enb*[1],
clav[1],
addr = 6
enb*[1],
clav[1],
addr = 6
enb*[0],
clav[0],
addr = 14
enb*[0],
clav[0],
addr = 14
enb*[0],
clav[0],
addr = 14
—
—
enb*[1],
clav[1],
addr = 3
—
enb*[0],
clav[0],
addr = 7
—
enb*[0],
clav[0],
addr = 7
enb*[0],
clav[0],
addr = 7
Port 15
—
—
enb*[3],
clav[3],
addr = 3
—
enb*[1],
clav[1],
addr = 7
—
enb*[0],
clav[0],
addr = 15
enb*[0],
clav[0],
addr = 15
Agere Systems Inc.
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