T8207 Datasheet, PDF (148/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
19 Timing Requirements (continued)
t1
WRITE_ACCESS_ACTIVE¹
t2
t3
t8
A[7:0]
D[7:0]
RDY_DTACK*²
t4
t6
t5
1. write_access_active is the logical OR function of sel*, wr*_ds*, and rd*_wr*.
2. Load is 50 pF.
Notes:
sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active signal.
rd*_wr* must be stable any time both sel* and wr*_ds* are low to prevent glitches on the write_access_active signals.
Figure 23. Motorola Mode Write Access Timing
t7
5-7789bF
t1
READ_ACCESS_ACTIVE¹
t2
t3
t11
A[7:0]
D[7:0]
RDY_DTACK*²
t4
t10
t9
t8
t6
t5
1. read_access_active is the logical OR function of sel*, wr*_ds*, and rd*_wr*.
2. Load is 50 pF.
Notes:
sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the read_access_active signal.
rd*_wr* must be stable any time both sel* and wr*_ds* are low to prevent glitches on the read_access_active signals.
Figure 24. Motorola Mode Read Access Timing
t7
5-7790bF
148
Agere Systems Inc.