T8207 Datasheet, PDF (41/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
8 Look-Up Table (continued)
8.5 Diagnostics
The T8207 also includes diagnostics to track misrouted cells. A cell is considered misrouted if its A and I bits are
“00,” if its VCI is out of range, or if the lutX_vpi_chk bit is ‘1’ and the unused VPI bits in the incoming cell header are
not all zero (see Section 8.3, Look-Up Procedure). When a misrouted cell is detected, the misrouted cell header
high and low registers (addresses 0146h and 0148h) may be updated. If enabled, the mis_cell interrupt, the vci_or
interrupt, or the vpi_or interrupt will be generated as appropriate (see Table 79 in Section 14.3, Extended Memory
Registers).
The misrouted cell header high and low registers contain the first four header bytes of selected misrouted cells.
Only a misrouted cell from a port whose mis_cell_lut_sel bit is set will update these registers, and this misrouted
cell will update the registers only if it is the first received after the mis_cell_clr bit is set. The lst_mis_cell_lut bits
indicate the port from which the header bytes in the misrouted cell header high and low registers were received.
The mis_cell_lut_sel bits are located in the misrouted LUT 1 register (address 0142h). The mis_cell_clr,
mis_cell_latch, and lst_mis_cell_lut bits are located in the misrouted LUT 2 register (address 0144h). (See Tables
70 and 71 in Section 14.3, Extended Memory Registers, for a complete description of the above bits.)
8.6 Setup
When configuring the lut_en bits in the LUT X configuration/status register (addresses 0320h through 033Eh), care
must be taken to ensure that the enabled ports’ LUTs correspond to the ports chosen in UTOPIA mode. (See Sec-
tion 9.6, UTOPIA Pin Modes.) If a LUT is not enabled, corresponding bits in the LUT X configuration structure
(Section 14.3.2.3, RX UTOPIA Monitoring, Table 103) will be ignored. Also, when the device is configured for UTO-
PIA PHY mode (see Section 9, UTOPIA Interface), only port 0 entries in the external RAM look-up table are used;
therefore, the look-up table should be set up accordingly.
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