T8207 Datasheet, PDF (135/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
14 Registers (continued)
14.3.3.1 SDRAM Control Memory
Table 119. Queue X Definition Structure (QXDEF) (2000h to 27E0h)
Name
base_addrX[24:9]
base_addrX[8:6]
Reserved
end_addrX[24:9]
end_addrX[8:6]
Reserved
wr_pntX[24:9]
wr_pntX[8:6]
Reserved
rd_pntX[24:9]
rd_pntX[8:6]
Reserved
fecn_fillX[24:9]
fecn_fillX[8:6]
Reserved
clp_fillX[24:9]
clp_fillX[8:6]
Reserved
Offset Bit Pos. Type Reset
Description
00h 15:0 RW X Base Address Queue X [24:9]. These bits configure the upper
16 bits of the queue’s base address offset in increments of one cell
(64 bytes).
02h 15:13 RW
Base Address Queue X [8:6]. These bits configure bits 6 through
8 of the queue’s base address offset in increments of one cell
(64 bytes).
12:0 RO
Reserved.
04h 15:0 RW
End Address Queue X [24:9]. These bits configure the upper
16 bits of the queue’s end address offset in increments of one cell.
The total number of cells held by the queue may be calculated by
subtracting the base_addr from the end_addr and adding one to the
difference. The minimum size of any queue is four cells.
06h 15:13 RW
End Address Queue X [8:6]. These bits configure bits 6 through 8 of
the queue’s end address offset in increments of one cell. The total
number of cells held by the queue may be calculated by subtracting
the base_addr from the end_addr and adding one to the difference.
The minimum size of any queue is four cells.
12:0 RO
Reserved.
08h 15:0 RW
Write Pointer for Queue X [24:9]. These bits must be initialized to
the base_addrX[24:9] before the queue is enabled.
0Ah 15:13 RW
Write Pointer for Queue X [8:6]. These bits must be initialized to the
base_addrX[8:6] before the queue is enabled.
12:0 RO
Reserved.
0Ch 15:0 RW
Read Pointer for Queue X [24:9]. These bits must be initialized to
the base_addrX[24:9] before the queue is enabled.
0Eh 15:13 RW
Read Pointer for Queue X [8:6]. These bits must be initialized to the
base_addrX[8:6] before the queue is enabled.
12:0 RO
Reserved.
10h 15:0 RW X FECN Fill for Queue X [24:9]. These bits with fecn_fillX[8:6] deter-
mine the queue’s fill level in cells (64 bytes) where the FECN bit is
set in outgoing cells. The FECN bit is set only when the
queueX_fecn_en bit is ‘1.’
12h 15:13 RW
FECN Fill for Queue X [8:6]. These bits with fecn_fillX[24:9] deter-
mine the queue’s fill level in cells (64 bytes) where the FECN bit is
set in outgoing cells. The FECN bit is set only when the
queueX_fecn_en bit is ‘1.’
12:0 RO
Reserved.
14h 15:0 RW
CLP Fill for Queue X [24:9]. These bits with clp_fillX[8:6] determine
the queue’s fill level in cells (64 bytes) where incoming cells with their
CLP bit set will be discarded. The incoming cell is dropped at this fill
level only when the queueX_clp_en bit is ‘1.’
16h 15:13 RW
CLP Fill for Queue X [8:6]. These bits with clp_fillX[24:9] determine
the queue’s fill level in cells (64 bytes) where incoming cells with their
CLP bit set will be discarded. The incoming cell is dropped at this fill
level only when the queueX_clp_en bit is ‘1.’
12:0 RO
Reserved.
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