T8207 Datasheet, PDF (90/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
14 Registers (continued)
14.2.3 General-Purpose I/O Control Registers
Table 47. GPIO Output Enable (GPIO_OE) (39h)
Name
Bit Pos.
GPIO_oe[7:0] 7:0
Type
RW
Reset
Description
0 GPIO Output Enable. If this bit is set to ‘1,’ the corresponding GPIO
pin is an output. If cleared to ‘0,’ the corresponding GPIO pin is an
input.
Table 48. GPIO Output Value (GPIO_OV) (3Bh)
Name
Bit Pos.
GPIO_out[7:0] 7:0
Type
RW
Reset
Description
0 GPIO Output Buffer. Output bits for the GPIO[7:0] pins are written to
this buffer. A bit in this buffer is only written to the pin if the corre-
sponding output enable bit is high.
Table 49. GPIO Input Value (GPIO_IV) (3Dh)
Name
Bit Pos. Type Reset
Description
GPIO_in[7:0] 7:0 RO 0 GPIO Input Buffer. This buffer contains the values at the GPIO[7:0]
pins.
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